博碩士論文 92521037 詳細資訊




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姓名 賴敬文(Ching-Wen Lai)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
(Design of Low-Jitter Adaptive Bandwidth PLL Based on Self-Biased Techniques)
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摘要(中) 隨著超大型積體電路設計在速度的效能上快速的增加,而現在的單位面積中所包含的電晶體越來越多,所導致的延遲相對提昇,在晶片組設計中精確的時序脈波是必須的,尤其目前朝向單晶片系統設計(System-On-a-Chip Design),在不同的子電路方塊當中常常會發生工作相位不同,或時脈偏斜(clock skew)所造成時脈不同步現象而嚴重威脅系統運作的正確性,而有誤動作的情況發生,因此,在主時脈進入子電路方塊之前通常會利用鎖相迴路(PLL)作相位校準的動作,使得所有晶片內各子電路的工作時脈同相位。
而鎖相迴路在設計上最大的挑戰,除了像低抖動(low jitter)、快速鎖定、低功率消耗等效能上的改善外,固定的電路參數限制使得一般的鎖相迴路僅能使用在特定規格上系統,降低了其應用性。而頻寬(Wn)、相位邊限(phase margin)和阻尼因素(damping factor)等等系統參數,決定了鎖相迴路整個系統的抖動(jitter)和穩定度(stability)。本論文針對鎖相迴路電路上的限制,利用數學公式的推導,找出迴路參數間的關係,再利用Time to Digital Converter (TDC)、programmable current mirror等外加電路,設計出具有寬範圍操作的鎖相迴路。頻寬可隨不同的狀態去調整,使抖動的影響降到最低;而相位邊限和阻尼因素的固定可確保鎖相迴路的穩定性。
本篇論文以TSMC 0.18μm 1P6M CMOS 製程來實現,工作電壓為1.8V。鎖相迴路的輸入參考頻率為5MHz-100MHz,輸出的操作頻率為100MHz-1GHz,週期抖動(period jitter)均小於輸出頻率的1.8%,而在操作頻率為1GHz、除頻器除數為200的狀態下,功率消耗為26.86mW。
摘要(英) When the efficiency of the speed with the very large-scale integrated (VLSI) circuit increases fast, there are more and more transistors in the unit area, because of these, the timing delay is promoted relatively. The accurate clock is necessary in chip design, especially the SOC (System-On-a-Chip Design ) is developed, however, there is often phase error or clock skew which generates asynchronous phenomenon in different sub-circuit blocks, and it always causes mistakes to affect accuracy of the system. In this reason, the phase locked loop (PLL) is used to correct the clock phase when the major clock inputs the sub-circuit, and it can lead the operation clock of the sub-circuit into the same clock phase.
The challenge in designing the PLL, besides the improvement of the performance like low jitter, fast locking, and low power consumption, the restrictions of fixed loop parameters make the normal PLL just used in the specific standards, and that reduces the applications of the PLL. The loop parameters such as loop bandwidth, phase margin and damping factor must be adjusted to minimize jitter and to guarantee stability. According to the restrictions of the PLL, this thesis employs formula derives to find the relationship between the loop parameters. Furthermore, we use time to digital converter (TDC), programmable current mirror (PCM) to design a PLL that has wide range applications. In the proposed circuit, the loop bandwidth can adjust in different states, and the fixed phase margin and damping factor can keep the stability of the PLL.
We use the TSMC 0.18μm 1P6M CMOS process with 1.8-volt supply voltage in this thesis. The input reference frequency is 5MHz-100MHz, the output operation frequency is 100MHz-1GHz, and the period jitter is less than 1.8% of the output frequency. The power consumption of the proposed PLL is 26.86mW at 200 multiplication factor, 1GHz operation frequency.
關鍵字(中) ★ 鎖相迴路
★ 寬範圍操作
關鍵字(英) ★ wide range
★ adaptive bandwidth
★ pll
論文目次 Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Function of The Adaptive Bandwidth 2
1.3 Thesis Overview 3
Chapter 2 The Concept of Phase-Locked Loop 4
2.1 PLL Background Theory 4
2.2 PLL Building Blocks 5
2.2.1 Phase Frequency Detector (PFD) 5
2.2.2 Charge Pump (CP) 7
2.2.3 Loop Filter (LF) 8
2.2.4 Voltage-Controlled Oscillator (VCO) 9
2.2.5 Frequency Divider (FD) 10
2.3 High Performance PLL Examples 11
2.3.1 A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop 12
2.3.2 A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation 14
2.3.3 Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL 17
Chapter 3 Adaptive Bandwidth PLL Design Flow 21
3.1 PLL Linear Model Analysis 21
3.1.1 Third Order PLL Model 22
3.1.2 PLL Behavioral Model Simulation 26
3.2 PLL Noise Sources Analysis 28
3.3 Operating Principle of The Proposed PLL 30
3.3.1 Quantitative Analysis of The Proposed PLL 30
3.3.2 Design Strategy of The Proposed PLL 33
3.4 Behavior Model Simulation of The Proposed PLL 35
3.5 Summary 38
Chapter 4 Adaptive Bandwidth PLL Circuit Realization 39
4.1 Architecture of The Proposed PLL 39
4.1.1 Phase Frequency Detector (PFD) 40
4.1.2 Charge Pump (CP) 42
4.1.3 Voltage Controlled Oscillator (VCO) 44
4.1.4 Loop Filter (LF) 47
4.1.5 Programmable Divider (PD) 48
4.1.6 Time to Digital Converter (TDC) 50
4.1.7 Programmable Current Mirror (PCM) 53
4.2 Simulation Results and Layout 54
4.2.1 Output Frequency: 100MHz; Multiplication Factor: 5, 20 54
4.2.2 Output Frequency: 500MHz; Multiplication Factor: 5, 100 56
4.2.3 Output Frequency: 1GHz; Multiplication Factor: 10, 200 58
4.2.4 Layout and the Specification Table 60
Chapter 5 Conclusions and Future Works 63
References 64
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指導教授 鄭國興(Kuo-Hsing Cheng) 審核日期 2005-7-20
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