|| Christian Enz, “An MOS transistor model for RF IC design valid in all regions of operation,” IEEE Transactions on Microwave Theory and Techniques, Vol. 50, pp. 342–339, Jan 2002.|
 Steve Hung-Min Jen, Christian C. Enz, David R. Pehlke, Michael Schroter and Bing J. Sheu, “Accurate modeling and parameter extraction for MOS transistors valid up to 10GHz,” IEEE Transactions on Electron Devices, vol. 11, pp. 2217-2227, Nov. 1999.
 H. W. Lin, S. S. Chung, S. C. Wong, and G. W. Huang, “An accurate RF CMOS gate resistance model compatible with HSPICE,” in Proc. IEEE 2004 Int. Conference on Microelectronic Test Structure, Vol. 17, pp. 227-230, Mar 2004.
 Yuhua Cheng, Chih-Hung Chen, Christian Enz, Mishel Matloubian and M. Jamal Deen, “MOSFET modeling for RF circuit design,” in Proceedings of the Third IEEE International Caracas Conference on Devices, Circuits and Systems (ICCDCS 2000), Cancun, Mexico, pp. D23, 1 - 8.
 A. J. Scholten, R. van Langevelde, L. F. Tiemeijer, R. J. Havens, and D.B. M. Klaassen, “Compact MOS modeling for RF CMOScircuit simulation,” in Simulation of Semiconductor Processes and Devices (SISPAD), 2001, pp. 194–201.
 Ickjin Kwon, Minkyu Je, Kwyro Lee, and Hyungcheol Shin, “A simple and analytical parameter-extraction method of a microwave MOSFET,” IEEE Transactions on Microwave Theory and Techniques, Vol. 50, No. 6, pp. 1503–1509, Jun 2002.
 BSIM3v3.2.2 MOSFET Model Users’ Manual, Department of Electrical Engineering and Computer Science, University of California, CA, 1999
 Subhash C. Rustagi, Huailin Liao, Jinglin Shi, Yong Zhong Xiong, “BSIM3 RF models for MOS transistors: A novel technique for substrate network extraction,” in IEEE International Conference on Microelectronics Test Structures (ICMTS), 17-20 March, 2003, pp. 118-123.
 J.C. Guo, C. H. Huang, K. T. Chan, W. Y. Lien, C. M. Wu, and Y. C. Sun, “0.13μm low voltage logic base RF CMOS technology with 115GHz fT and 80GHz fMAX,” 33rd European Microwave Conference, pp. 682-686, 2003.
 Sang M. Nam, Byung J. Lee, Sung H. Hong, Chong G. Yu, Jong T. Park and Hyun K. Yu, “Experimental investigation of temperature dependent RF performances of RF-CMOS devices,” in 6th International Conference on IC and CAD (ICVC '99), pp.174-177, Oct., 1999, Seoul, Korea.
 Mitiko Miura-Mattausch, “MOSFET modeling for RF-CMOS design,” IEEE, pp. 482-490, 2004.
 J. J. Ou, X. Jin, I. Ma, C. Hu and P. R. Gray, “CMOS rf modeling for GHz communication IC’s,” in 1998 Symposium on VLSI Technology Digest, pp. 94-95, 1998.
 E. Abou-Allam and T. Manku, “A small-signal MOSFET model for radio frequency IC application,” IEEE Tansactions on Electron Device, pp. 2217-2226, 1999.
 K.W. Chew, K.S. Yeo, S.-F. Chu and Y.M. Wang, “Impact of 0.25μm dual gate thickness CMOS process on flicker noise performance of multifingered deep-submicron MOS device,“ in IEE Proc.-circuits Devices Syst., Vol. 148, No. 6, pp 312-317, Dec 1999.
 M.C. King, Z.M. Lai, C.H. Huang, C.F. Lee, M.W. Ma, C.M. Huang, Yun Chang and Albert Chin, “Modeling finger number dependence on RF noise to 10GHz in 0.13μm node MOSFETs with 80nm gate length,” in 2004 IEEE radio frequency integrated circuit symposium, pp. 171-174, 2004.
 Pierre H. Woerlee, Mathijs J. Knitel, Ronald van Langevelde, Dirk B. M. Klaassen, Luuk F. Tiemeijer, Andries J. Scholten and Adrie T.A. Zegers-van Duijnhoven, “RF-CMOS performance trends,” IEEE Trans. Electron Devices, vol. 48, No. 8, pp. 1776-1782, 2001.
 T. Boutchacha, G. Ghibaudo and B. Belmekki, “Study of low frequency noise in the 0.18μm silicon CMOS transistors,” in Proc. IEEE 1999 Int. Conf. on Microelectronic Test Stuctures, Vol. 12, pp. 84-88, 1999.
 Yi Lin, Michael Obrecht and Tajinder Manku, “RF noise characterization of MOS devices ofr LNA design using a phsucal-based quasi-3-D approach,” IEEE trans. Circuits and system-II: Analog and digital signal processing, Vol. 48, No. 10, pp. 972-984, Oct 2001.
 C. H. Huang, C. H. Lai, J. C. Hsieh, J. Liu and A. Chin, “Rf noise in 0.18-?m and 0.13-?m MOSFETs,” IEEE Microwave and Wireless Components Lett.. vol. 12, pp. 464-466, 2002.
 Alfredo Arnaud and Carlo Galup-Montoro, “A compact model for flicker noise in MOS transistors for analog circuit design,” IEEE Trans. Electron Devices, vol. 50, pp. 1815-1818, 2003.
 C. S. Kim, H. K. Yu, H. Cho, S. Lee and K. S. Nam, “Critical discussion on unified 1/f noise models for MOSFETs,” IEEE, 2003.
 L. K. J. Vandamme, Xiaosong Li and Dominique Rigaud, “1/f noise in MOS devices, mobility or number fluctuations,” IEEE Trans. Electron Devices, vol. 41, pp. 1936-1945, 1994.
 Yuhua Cheng, Chih-Hung Chen, Mishel Matloubian and M. Jamal Deen, “High frequency small signal AC and noise modeling of MOSFETs for RF IC design,” IEEE Trans. Electron Devices, vol. 49, pp. 400-408, 2002.
 Kenneth K. O, Namkyu Park and Dong-Jun Yang, “1/f noise of NMOS and PMOS transistors and their implications to design of voltage controlled oscillators,” in 2002 IEEE Radio Frequency Integrated Circuit Symposium, 2002.
 Jacques Zimmermann and Gerard Ghibaudo, “Static and noise characterization of deep submicron CMOS devices”, IEEE, pp. 521-529, 1995.
 K.K. Hung, P.K. Ko, C. Hu and Y.C. Cheng, “Flicker noise characteristics of advanced MOS technology”, in IEDM Tech. Dig., 1988.
 Fan-Chi Hou, Gijs Bosman and Mark E. Law “Simulation of oxide trapping noise in submicron n-channel MOSFETs”, IEEE Trans. Electron Devices, vol. 50, pp. 846-852, 2003.
 F. M. Klaasen, “High frequency noise of the function field-effect transistor”, IEEE Trans. on Electron Devices, vol. 14, no. 7, pp.368-373, 1967.
 Andries J. Scholten, Luuk F. Tiemeijer, Ronald van Langevelde, Ramon J. Havens, Adrie T.A. Zegers-van Duijnhoven and Vincent C. Venezia, “Noise modeling for RF CMOS circuit simulation”, IEEE Trans. on Electron Devices, vol. 50, no. 3, pp. 618-632, 2003.
 Udo Karthaus and Martin Fischer, “Fully integrated passive UHF RFID transponder IC with 16.7-?W minimum RF input power”, IEEE Journal of solid-state circuit, vol. 38, no. 10, pp. 1602-1608, Oct. 2003.
 Joon H. Kim, Ji H. Kim, Youn S. Noh, Young S. Kim, Song G. Kim and Chul S. Park, “An MMIC smart power amplifier of 21% PAE at 16dBm power level for W-CDMS mobile communication terminals”, in 2002 IEEE GaAs Digest, pp. 181-184, 2002.
 Ravi Gupta, Brian M. Ballweber and David J. Allstot, “Design and optimization of CMOS RF power amplifiers”, IEEE Journal of Solid-State Circuits, vol. 35, no. 2, pp. 166-175, Feb. 2001.
 Hafez Fouad, Khaled Sharaf, Essam El-Diwany, and Hadia El-Hennawy, “An RF CMOS modified-cascode LNA with inductive source degeneration”, in 19th National Tadio Science Conference, Alexandria, pp.450-457, Mar. 2002.
 M. Kumarasamy Raja, Terry Tear Chin Boon, K.Nuntha Kumar and Wong Sheng Jau, “A fully integrated variable gain 5.75GHz LNA with on chip active Balun for WLAN”, in 2003 IEEE Radio Frequency Integrated Circuit Symposium, pp. 439-442, IEEE, 2003.
 B. Razavi, Design of analog CMOS integrated circuits, McGraw-Hill Inc, New York, 2001.
 B. Razavi, RF microelectonics, PreTEX Inc, USA, 1998.
 Klaus Finkenzeller, RFID HANDBOOK, John Wiley & Sons Ltd, 1999.
 Trond Ytterdal, Yuhua Cheng, Tor A. Fjeldly, Device Modeling for Analog and RF CMOS Circuit Design, John Wiley & Sons Ltd, 2003.
 M. Kumarasamy Raja, Terry Tear Chin Boon, K.Nuntha Kumar and Wong Sheng Jau, “Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures”, IEEE Trans. on Electron Devices, vol. 41, no. 11, pp. 1965-1971, NOV 1994.
 Ray Jayaraman, Charles G. Sodini, “A 1/f noise technique to extract the oxide trap density near conduction band edge of Silicon”, IEEE Trans. on Electron Devices, vol. 36, no. 9, pp. 1773-1782, SEP 1989.