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姓名	林信佑(Shin-Yo Lin)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	應用於無線通訊系統之同質性可組態記憶體式快速傅立葉處理器 (Homogeneous Reconfigurable Memory-based FFT Processor for Wireless Communication Systems)
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摘要(中)	在通訊領域的信號處理中，快速地發展其通訊規格及格式，並能夠隨著環境的變化而發展出適應性的演算法之趨勢，需要具備高彈性度的演算法及低複雜度的硬體設計之兩大可程式化的解決方案。近年來，擁有多規格的無線通訊之產品，被要求具有高運算能力、高靈活性、及高擴充性之能力，可組態式架構在過去，儼然已經證明在靈活性、實現的複雜性、和能源效率之間，成功的展現出一折衷的解決方案。 在這篇論文中，我們分析了幾種快速傅立葉(Fast Fourier Transform)演算法的複雜性及其硬體架構設計。在傳統的架構中，它可分為管道式(pipeline)和記憶體式(memory-based)兩種架構，管道式的優點是有更高的吞吐量(throughput)和控制單元簡單之優點，但其硬體面積較大；而記憶體式架構則反之。 本論文提出一同質性可組態記憶體式快速傅立葉處理器，適合應用於多樣化的無線通訊系統中。我們重新檢視radix-2 快速傅立葉演算法，並重新探討傳統的信號流程圖(Signal Flow Graph, SFG)，進而發展出另一種信號流程圖的表示法，其中我們證明了輸入資料的改變，並不會喪失原有的快速傅立葉數學運算性。因此，這樣的信號流程圖表示法，可以容易地得到一同質性之運算並行式結構的可組態式快速傅立葉處理器之架構，藉以提高吞吐量。同時，仍保有記憶體式架構優於管線式架構面積小的優勢，提昇原有記憶體式架構之速度，且易於控制。本論文所提出之同質性可組態記憶體式快速傅立葉處理器，可以容易的擴展至任何N=2^r的點數，且可任意的調整此架構，以實現快速傅立葉處理器的效率。最後，我們利用此同質性可組態記憶體式快速傅立葉處理器之架構，驗證於超寬帶 (UWB) 和第二代地面數位視頻廣播 (DVB-T2) 系統，以呈現此架構之彈性的可組態性。
摘要(英)	Current trends in the field of signal processing for communications include rapidly evolving standards, formats, and algorithms that adapt to dynamic factors in the environment. These trends require programmable solutions that possess both algorithm flexibility and low implementation complexity. Current multi-standard wireless communication applications demand high-computing power, flexibility, and scalability. Reconfigurable architectures demonstrate excellent tradeoffs between algorithm flexibility, implementation complexity, and energy efficiency. This thesis analyzes several types of complexity and the hardware architecture designs of FFT algorithms. The traditional structure can be divided into pipeline and memory-based architectures. The former has the strengths of higher throughput and easier control unit, but its hardware area is larger. The latter has the opposite strengths and weaknesses. This dissertation presents a reconfigurable homogeneous memory-based FFT processor architecture integrated in a single chip to enable diverse wireless communication systems. Specifically, this thesis reinvestigates a radix-2 FFT algorithm and rearranges an alternative signal flow graph (SFG) from conventional SFGs. By developing the alternative SFG, this thesis proves that the altered permutation of input data can maintain the original functionality of FFT computation. Consequently, the alternative SFG is readily realized as the architecture of homogeneous parallel structure with multiple processing elements to increase throughput. However, the proposed design retains the advantage of a small area for the memory-based architecture, and achieves the goals of fast operation and ease of control. The proposed homogeneous structure is suitable for any N=2^r FFT. The structure can also be adjusted based on the desired application, achieving an efficient FFT processor. This thesis validates the homogenous structure on ultra-wideband (UWB) and digital video broadcasting-second generation terrestrial (DVB-T2) systems, and shows that the proposed design offers flexible reconfigurability.
關鍵字(中)	★ 同質性 ★ 可組態 ★ 記憶體式快速傅立葉處理器	關鍵字(英)	★ Homogeneous ★ Reconfigurable ★ Memory-based FFT processor
論文目次	摘要 III ABSTRACT IV 致謝 V CHAPTER 1 INTRODUCTION 1 1.1 Background 1 1.2 Motivation 6 1.3 Organization of Dissertation 8 CHAPTER 2 OVERVIEW OF EXISTING FAST FOURIER TRANSFORM ALGORITHMS AND ARCHITECTURES 9 2.1 The FFT Algorithms 11 2.1.1 Radix-2 DIF FFT Algorithm 11 2.1.2 Symmetry Property of Twiddle Factors 14 2.1.3 Radix-4 DIF FFT Algorithm 15 2.1.4 Radix-8 DIF FFT Algorithm 16 2.1.5 Split-Radix 2/4 FFT Algorithm 17 2.1.6 Split-Radix 2/8 FFT Algorithm 19 2.2 The FFT Architectures 21 2.2.1 Pipeline-Based FFT Architecture 21 2.2.2 Memory-Based FFT Architecture 26 2.2.2.1 In-Place Memory Management 28 2.3 Summary 31 CHAPTER 3 HOMOGENEOUS PARALLEL MEMORY-BASED FFT PROCESSOR DESIGN 33 3.1 One PE MBFFT Processor Development 34 3.1.1 SFG Representation 34 3.1.2 Input Data Grouping Algorithm 40 3.1.3 MBFFT1 Architecture 48 3.2 Parallel MBFFT (MBFFTP2w) Processor Development 55 3.2.1 MBFFTP2 Architecture 55 3.2.2 MBFFTP4 Architecture 56 3.2.3 MBFFTP2w Architecture 57 3.3 Summary 59 CHAPTER 4 RECONFIGURABLE MBFFT PROCESSOR DESIGN 61 4.1 Reconfigurable MBFFTP2 Processor 62 4.2 Reconfigure MBFFTP4 Processor 63 4.3 Reconfigurable MBFFTP2w Processor 65 4.4 Possible SISO/MIMO Application 68 4.5 Summary 73 CHAPTER 5 VALIDATION ON COMMUNICATION APPLICATIONS 75 5.1 Ultra-Wideband (UWB) System 76 5.1.1 Design Requirements 80 5.1.2 CF-MBFFTP4 Processor Design 82 5.1.3 Chip Implementation and Measurement 88 5.1.4 Performance Comparison 91 5.1.5 Summary 93 5.2 Digital Video Broadcasting – Second Generation Terrestrial (DVB-T2) System 94 5.2.1 Design Requirements 96 5.2.2 MBFFTP4 Processor Design 97 5.2.3 Implementation 104 5.2.4 Performance Comparison 106 5.3 Summary 108 CHAPTER 6 CONCLUSIONS AND FUTURE WORKS 111 REFERENCE 113 PUBLICATIONS 123
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指導教授	魏慶隆、蔡佩芸 (Chin-Long Wey、Pei-Yun Tsai)	審核日期	2012-1-16
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