奈米尺度薄膜轉移技術

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：29

、訪客IP：52.15.153.23

姓名

張朝喨(Chao-Liang Chang) 查詢紙本館藏

畢業系所

機械工程學系

論文名稱

奈米尺度薄膜轉移技術
(A nano-thick layer transfer technology)

相關論文

★ 塑膠機殼內部表面處理對電磁波干擾防護研究	★ 研磨頭氣壓分配在化學機械研磨晶圓膜厚移除製程上之影響
★ 利用光導效應改善非接觸式電容位移感測器測厚儀之研究	★ 石墨材料時變劣化微結構分析
★ 半導體黃光製程中六甲基二矽氮烷之數量對顯影後圖型之影響	★ 可程式控制器機構設計之流程研究
★ 伺服沖床運動曲線與金屬板材成型關聯性分析	★ 鋁合金7003與630不銹鋼異質金屬雷射銲接研究
★ 應用銲針尺寸與線徑之推算進行銲線製程第二銲點參數優化與統一之研究	★ 複合式類神經網路預測貨櫃船主機油耗
★ 熱力微照射製作絕緣層矽晶材料之研究	★ 微波活化對被植入於矽中之氫離子之研究
★ 矽/石英晶圓鍵合之研究	★ 光能切離矽薄膜之研究
★ 氮矽基鍵合之研究	★ 以氫離子擴散機制製作單晶矽薄膜在石英上之研究

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 ( 永不開放)

摘要(中)

自從電晶體發明以來，電子元件(Device)逐年的減少尺寸大小與增快調變速度已成為既定的目標，由於電晶體發展如此快速，不僅帶動半導體產業發展，更加速資訊、通訊等相關產業蓬勃發展。絕緣層矽晶(Silicon on Insulator；SOI技術)是一種與CMOS的隔離有關的新技術，今日CMOS元件已進入小於100奈米領域，寄生電容的效應亦不可忽視，使絕緣層矽晶結構的特殊優點有發揮的空間，而逐漸受到各方的矚目與研究。至今為何絕緣層矽晶圓未被普遍使用，主要是受限於絕緣層矽晶圓的品質與價格，由於近年來，有各種不同的絕緣層矽晶圓製作方法提出，使得品質與價格已獲得大幅度的改善。
本研究主要是利用Smart Cut和BESOI的技術並改善其兩者缺點，得到奈米單晶絕緣層矽晶結構。實驗方法為利用LPCVD方式在氧化層上增加多晶矽犧牲層，改變離子進入基材深度，獲得小於100奈米的單晶矽層進行剝離，並完整的移除多晶矽犧牲層，降低其需鍵合面的表面粗糙度，克服了經過離子佈植後的多晶矽犧牲層表面粗糙度甚大問題，得以直接鍵合，最後經由薄膜轉移，不需經過減薄製程，即可得到100nm的奈米單晶絕緣層矽晶。

摘要(英)

As CMOS devices scale down to 90nm node or below, parasitic capacitance and low current leakage will increase. Therefore, the unique properties of silicon-on-insulator (SOI) structure are able to solve above problems, because SOI wafers consist of a layer of single crystalline Si that is separated from Si substrate by an insulating film of SiO2. Building IC devices in this top Si film effect many advantages such as reducing capacitance and leakage and no latch-up , especially for the design of high speed and low power consumption devices. The issue of quality of massive production doesn’t also make SOI wafers a mainsfrain material to substitute for bulk silicon. But numerous advanced SOI fabricating techniques have been invented nowadays; all these will upgrade the quality and lessen the price of SOI wafers.
In this study, one dimensional nanostructure materials on a desired substrate fabricated by a hydrogen ion-exfoliation-based wafer bonding approach. The nano-scale defining thickness is exactly achieved by the employment of polysilicon depth as implant sacrificial layer. After hydrogen ion implantation, the as-implanted wafer was contained a hydrogen-rich buried layer less than 100 nm. Prior to the as-implanted wafer being bonded with a handle wafer, the polysilicon layer was removed by a wet chemical etching method. A nanothick single crystal silicon layer was than thermal successfully transferred from a device wafer onto a handle wafer after 10-minute microwave irradiation. The thickness of the final transferred silicon layer measured by transmission electron microscopy (TEM) was 100 nm.

關鍵字(中)

★ 離子佈植
★ 非等向性蝕刻

關鍵字(英)

★ Anisotropic Etching
★ Ion implantation

論文目次

總目錄
摘要-----------------------------------------------------Ⅰ
英文摘要-------------------------------------------------Ⅱ
謝誌-----------------------------------------------------Ⅲ
總目錄---------------------------------------------------Ⅳ
圖目錄---------------------------------------------------Ⅵ
表目錄---------------------------------------------------Ⅷ
第一章緒論-----------------------------------------------1
1.1 研究背景----------------------------------------1
1.2 研究動機----------------------------------------3
第二章薄膜沉積與蝕刻機制---------------------------------9
2.1結晶矽薄膜沉積----------------------------------9
2.2結晶矽蝕刻機制---------------------------------13
2.3多晶矽蝕刻-------------------------------------22
2.3.1多晶矽蝕刻流程----------------------------22
2.3.2實驗儀器----------------------------------23
2.4實驗結果與討論---------------------------------25
2.4.1 沉積後狀況-------------------------------25
2.4.2 蝕刻後表面狀況---------------------------25
第三章奈米單晶絕緣層矽晶製作----------------------------40
3.1 奈米單晶絕緣層矽晶製作流程--------------------40
3.2 實驗儀器--------------------------------------42
3.3 SRIMTM模擬分析---------------------------------43
3.4 薄膜分離之比較與單晶矽薄膜分析----------------44
第四章結論---------------------------------------------49
參考資料
論文發表

參考文獻

[1]吳憲昌,陳啟東, ”單電子電晶體的進展與應用”自然科學簡訊第十五卷第四期,pp115-118(2003)
[2]G.K. Celler, “Applied physics reviews-focused review: Frontiers of silicon-on-insulator”, J. of Appl. Phys., Vol.93, No.9, pp4955-4975 (2003)
[3]Hong Xiao, “Introduction to Semiconductor Manufacturing Technology”, Prentice-Hall Inc., pp53-299 (1992)
[4]莊達人,“VLSI製造技術”, 高立圖書有限公司, pp74-578 (2004)
[5]James B. Kuo,Ker-Wei Su, CMOS VLSI ENGINEERING :Silicon-on-Insulator (SOI), Kluwer Academic Publishers, pp1~11 (1998)
[6]Hitoshi Habuka, “Roughness of Silicon Suface Heated in Hydrogen Ambient” ,J. Electrochem. Soc, Vol. 142, No.9, pp3092-3097(1995).
[7]Julian Blake, “SIMOX (Separation by Implantation of Oxygen)”, Encyclopedia of Physical Science and Technology, third edition, Volume 14, pp805-813(2001)
[8] Tien-Hsi Lee, “Semiconductor thin film transfer by wafer bonding and advanced ion implantation layer splitting technologies”, Duke University, pp100-121 (1998)
[9] Q. -Y. Tong et al., Semiconductor Wafer Bonding: Science and Technology, John Wiley＆Sons, Inc. pp141-149 (1999)
[10]M. Bruel, “Silicon on insulator material technology ” , Electron. Lett., Vol.31, pp1201(1995)
[11]Christophe Maleville and Carlos Mazure, “Smart-Cut® technology: from 300 mm ultrathin SOI production to advanced engineered substrates”, Solid-State Electronics, Vol. 48, pp1055–1063(2004)
[12]黃惠良,”微電子工程”,五南出版社,pp151-152(民89)
[13]白木靖寬,吉田貞史著,王建義譯,”薄膜工程學”,全華出版社,pp4-60-4-61(民93)
[14]Tien-His Lee,“Manufacturing Method of Thin Film on a substrate”,00452866(2001)
[15]Kazuo Sato, et al.,” Anisotropic etching rates of single-crystal silicon for TMAH water solution as a function of crystallographic orientation”, Sensors and Actuators 73,pp131–137(1999)
[16]Chii-Rong Yang et al,” Effects of mechanical agitation and surfactant additive on silicon anisotropic etching in alkaline KOH solution”, Sensor and Actuators A 119,pp263-270(2005)
[17]W. Lang,” Silicon microstructuring technology”, Mater. Sci. Eng. R 17,pp 1–55(1996)
[18]陳炳煇,”微機電系統”,五南圖書出版公司,pp55-118(民90)
[19]E.D. Palik, O.J. Glembocki, I. Heard, P.S. Burno, L. Tenerz, “Etching roughness for (1 0 0) silicon surfaces in aqueous KOH”, J. Appl. Phys.70 (6) pp3291–3300 (1991).
[20]T. Baum, D.J. Schiffrin, “AFM study of surface finish improvement by ultrasound in the anisotropic etching of Si <1 0 0> in KOH for micromachining applications, J. Micromech. Microeng. 4,pp338–342 (1997)
[21]S.A. Campbell, K. Cooper, L. Dixon, R. Earwaker, SN. Port, “Inhibition of pyramid formation in the etching of Si <1 0 0> in aqueous potassium hydroxide–isopropanol”, J. Micromech. Microeng. 5 ,pp209–218(1995)
[22]Ping-Hei Chen,Hsin-Yah Peng,Chia-Ming Hsieh,Minking K. Chyu,”The characteristic behavior of TMAH water solution for anisotropic etching on both Silicon substrate and SiO2 layer”, Sensor and Actuators A 93,pp132-137(2001)
[23]Irena Zuubel, Malgorzata Kramkowska,”The effect of isopropyl alcohol on etching rate and roughess of (1 0 0) Si surface etched in KOH and TMAH solutions”,Sensors and Actuators A93,pp138-147(2001)
[24]行政院國科會精儀中心, ”微機電系統技術與應用”,國科會精儀中心,pp 864(民92)
[25] J.O. Borland,et al,”Influence of epi-substrate point defect properties on getter enhanced Si expitaxial processing for advanced CMOS and bipolar technologies”, VLSI Science and Technology 1984,K.E. Bean and G. Rozgonyi, Eds., J. Electrochem. Society, NJ,pp93(1984)
[26]W. Dyson, et al., N+ and P+ substrate effects on epitaxial silicon Properties”,VLSI Science and Technology 1984,K.E. Bean and G. Rozgonyi, Eds., J. Electrochem. Society, NJ,pp107(1984)
[27]Stephen D. Senturia, “Microsystem Design”, KLUWER ACADEMIC PUBLISHERS, pp61-65(2001)
[28]D. R. Ciarlo, “Corner compensation structures for (110) oriented silicon”, IEEE Micro Robots and Teleoperators Workshop, pp. 6/1-4 (1987)

指導教授

李天錫(Tien-Hsi Lee)

審核日期

2006-7-20

推文