博碩士論文 93323118 詳細資訊




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姓名 張朝喨(Chao-Liang Chang)  查詢紙本館藏   畢業系所 機械工程學系
論文名稱 奈米尺度薄膜轉移技術
(A nano-thick layer transfer technology)
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摘要(中) 自從電晶體發明以來,電子元件(Device)逐年的減少尺寸大小與增快調變速度已成為既定的目標,由於電晶體發展如此快速,不僅帶動半導體產業發展,更加速資訊、通訊等相關產業蓬勃發展。絕緣層矽晶(Silicon on Insulator;SOI技術)是一種與CMOS的隔離有關的新技術,今日CMOS元件已進入小於100奈米領域,寄生電容的效應亦不可忽視,使絕緣層矽晶結構的特殊優點有發揮的空間,而逐漸受到各方的矚目與研究。至今為何絕緣層矽晶圓未被普遍使用,主要是受限於絕緣層矽晶圓的品質與價格,由於近年來,有各種不同的絕緣層矽晶圓製作方法提出,使得品質與價格已獲得大幅度的改善 。
本研究主要是利用Smart Cut和BESOI的技術並改善其兩者缺點,得到奈米單晶絕緣層矽晶結構。實驗方法為利用LPCVD方式在氧化層上增加多晶矽犧牲層,改變離子進入基材深度,獲得小於100奈米的單晶矽層進行剝離,並完整的移除多晶矽犧牲層,降低其需鍵合面的表面粗糙度,克服了經過離子佈植後的多晶矽犧牲層表面粗糙度甚大問題,得以直接鍵合,最後經由薄膜轉移,不需經過減薄製程,即可得到100nm的奈米單晶絕緣層矽晶。
摘要(英) As CMOS devices scale down to 90nm node or below, parasitic capacitance and low current leakage will increase. Therefore, the unique properties of silicon-on-insulator (SOI) structure are able to solve above problems, because SOI wafers consist of a layer of single crystalline Si that is separated from Si substrate by an insulating film of SiO2. Building IC devices in this top Si film effect many advantages such as reducing capacitance and leakage and no latch-up , especially for the design of high speed and low power consumption devices. The issue of quality of massive production doesn’t also make SOI wafers a mainsfrain material to substitute for bulk silicon. But numerous advanced SOI fabricating techniques have been invented nowadays; all these will upgrade the quality and lessen the price of SOI wafers.
In this study, one dimensional nanostructure materials on a desired substrate fabricated by a hydrogen ion-exfoliation-based wafer bonding approach. The nano-scale defining thickness is exactly achieved by the employment of polysilicon depth as implant sacrificial layer. After hydrogen ion implantation, the as-implanted wafer was contained a hydrogen-rich buried layer less than 100 nm. Prior to the as-implanted wafer being bonded with a handle wafer, the polysilicon layer was removed by a wet chemical etching method. A nanothick single crystal silicon layer was than thermal successfully transferred from a device wafer onto a handle wafer after 10-minute microwave irradiation. The thickness of the final transferred silicon layer measured by transmission electron microscopy (TEM) was 100 nm.
關鍵字(中) ★ 離子佈植
★ 非等向性蝕刻
關鍵字(英) ★ Anisotropic Etching
★ Ion implantation
論文目次 總目錄
摘要-----------------------------------------------------Ⅰ
英文摘要-------------------------------------------------Ⅱ
謝誌-----------------------------------------------------Ⅲ
總目錄---------------------------------------------------Ⅳ
圖目錄---------------------------------------------------Ⅵ
表目錄---------------------------------------------------Ⅷ
第一章 緒論-----------------------------------------------1
1.1 研究背景----------------------------------------1
1.2 研究動機----------------------------------------3
第二章 薄膜沉積與蝕刻機制---------------------------------9
2.1結晶矽薄膜沉積----------------------------------9
2.2結晶矽蝕刻機制---------------------------------13
2.3多晶矽蝕刻-------------------------------------22
2.3.1多晶矽蝕刻流程----------------------------22
2.3.2實驗儀器----------------------------------23
2.4實驗結果與討論---------------------------------25
2.4.1 沉積後狀況-------------------------------25
2.4.2 蝕刻後表面狀況---------------------------25
第三章 奈米單晶絕緣層矽晶製作----------------------------40
3.1 奈米單晶絕緣層矽晶製作流程--------------------40
3.2 實驗儀器--------------------------------------42
3.3 SRIMTM模擬分析---------------------------------43
3.4 薄膜分離之比較與單晶矽薄膜分析----------------44
第四章 結論---------------------------------------------49
參考資料
論文發表
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指導教授 李天錫(Tien-Hsi Lee) 審核日期 2006-7-20
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