| 姓名 |
陳冠宇(Kuan-yu Chen)
查詢紙本館藏 |
畢業系所 |
化學工程與材料工程學系 |
| 論文名稱 |
氧化鋁模板法製備鎳金屬奈米線及其與(001)Si基材之界面反應研究
(Fabrication of nickel metal nanowire arrays by using AAO templates technique and the interfacial reactions of the Ni nanowires on (001)Si substrates)
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| 摘要(中) |
在本研究中將利用可被移除之陽極氧化鋁(anodic aluminum oxide, AAO)作為模板，以電化學沈積方式製作大面積且規則排列之鎳金屬奈米線，並研究鎳金屬奈米線於(001)Si基材上經不同溫度熱處裡後之界面反應。
利用控制陽極處理的條件，選用適當的電解液進行陽極處理，本實驗已成功在高純度的鋁片上製備出自我規則排列之奈米通道結構。利用改變電解液的組成、陽極處理之溫度與工作電壓，可以調變孔徑大小在20-100 nm之AAO模板。再利用電化學方式將鎳金屬沈積於奈米通道中，並將AAO模板移除後，即可得到大量且線寬均一之鎳金屬奈米線。進一步利用穿透式電子顯微鏡(TEM)與選區電子繞射(SAED)分析，可發現有部分鎳金屬奈米線為單晶結構，且這些單晶奈米線的成長方向與AAO之孔徑大小有關。利用孔徑大小為250 nm與50 nm之AAO模板鍍製出來的鎳金屬奈米線，其成長方向分別為<111>與<110>。
將50 nm鎳金屬奈米線置於(001)矽晶基材上退火至400 ℃，可以發現磊晶相的二矽化鎳(NiSi2)與複晶相的矽化鎳(NiSi)並存。此奈米尺度之鎳金屬線與矽晶基材反應時，二矽化鎳的生成溫度相較於薄膜結構所需要的溫度(~750 ℃)低了大約350 ℃，此結果顯示小尺寸之鎳金屬線較容易形成磊晶相之二矽化鎳。當溫度升高到500 ℃以上，可明顯的觀察到鎳矽化物奈米線之形態變化。這些磊晶形態之二矽化鎳發現有明顯的刻面(facet)，且這些刻面結構在高溫時更容易形成。經鑑定分析後這些磊晶相二矽化鎳之刻面結構形態呈現一倒金字塔型，且每個金字塔形態之二矽化鎳晶體均由一個{001}表面與四個{111}界面所組成。而經由比對選區電子繞射圖形，鑑定磊晶態之二矽化鎳與矽晶基材之磊晶關係為[001] NiSi2 // [001] Si 且 (200) NiSi2 // (400) Si。 |
| 摘要(英) |
In this study, the fabrications of large-area well-aligned nickel metal nanowire arrays by using the electrodeposition in conjunction with removable anodic aluminum oxide (AAO) templates technique, and the interfacial reactions of the Ni nanowires on (001)Si substrates after different heat treatments have been investigated.
Under controlled anodization conditions, self-ordered nanochannel structures were produced by anodization of high-purity aluminum sheets in appropriate acid solutions. The pore sizes of AAO templates can be tuned from 20 to 100 nm by varying the component of electrolyte, the processing temperature, and the applied anodic voltage. After electrodeposition of Ni into the nanochannels and subsequent removing the AAO templates, a large amount of Ni metal nanowires of same diameter were obtained. Based on TEM and selected-area electron diffraction (SAED) analysis, some of the prepared Ni nanowires were single crystalline and the growth directions of these Ni nanowires were found to be affected by the pore sizes of AAO templates. The dominate growth directions of the Ni nanowires produced from 250 nm and 50 nm pore sizes AAO templates were along the <111> and <110> crystal directions, respectively.
For the 50 nm Ni nanowires on (001)Si substrates after annealing at 400 ℃, epitaxial NiSi2 phase was found to coexist with the ploycrystalline NiSi phase. The nucleation temperature of NiSi2 phase in the nanoscale Ni wires/(001)Si samples was found to be lowered by about 350 ℃ compared to what is usually needed for the growth of NiSi2 (~750 ℃). The results revealed that the growth of epitaxial NiSi2 was more favorable for the miniature size Ni metal wires. For the samples annealed at 500 ℃ or above, morphological degradation of Ni silicide nanowires were evident. These epitaxial NiSi2 nanowires formed on (001)Si were found to be heavily faceted and the faceted structures were more prone to form at higher temperatures. The faceted structure of epitaxial NiSi2 was identified to be an inverse pyramid in shape, and each pyramidal-shaped NiSi2 dot was composed of one (001) surface and four {111} interfaces. Furthermore, from the analysis of the SAED patterns, the epitaxial orientation relationship between the NiSi2 and silicon substrates was identified to be [001] NiSi2 // [001] Si and (200) NiSi2 // (400) Si. |
| 關鍵字(中) |
★ 陽極氧化鋁
★ 電化學沈積
★ 電鍍
★ 界面反應
★ 鎳金屬奈米線
★ 矽化物 |
關鍵字(英) |
★ electrodeposition
★ silicide
★ ni nanowire
★ AAO |
| 論文目次 |
摘要I
AbstractIII
致謝V
目錄VI
圖目錄VIII
第一章 簡介1
1-1 前言1
1-2 陽極氧化鋁模板2
1-3 鎳金屬奈米線生成4
1-4 金屬矽化物6
1-5 半導體中金屬矽化物製程8
1-6 研究動機10
第二章 實驗步驟11
2-1 氧化鋁模板的製備11
2-11 使用草酸作為電解溶液之氧化鋁模板製備11
2-12 使用硫酸作為電解溶液之氧化鋁模板製備12
2-2 電化學沈積鎳金屬奈米線12
2-3 鎳金屬矽化物之生成13
2-31 矽晶試片清洗13
2-32 鎳金屬奈米線排列13
2-33 退火處理14
2-4 試片分析14
2-41 掃描式電子顯微鏡(SEM)14
2-42 原子力顯微鏡(AFM)14
2-43 穿透式電子顯微鏡與X光能量散佈光譜儀15
2-44高分辨穿透式電子顯微鏡15
第三章 結果與討論16
3-1 陽極氧化鋁模板16
3-11 以草酸為電解液製備氧化鋁模板16
3-12以硫酸為電解液製備氧化鋁模板18
3-2 電化學沈積鎳金屬奈米線19
3-3 鎳金屬奈米線與矽晶界面反應21
第四章 結論與未來展望25
4-1 結論25
4-2 未來展望26
參考文獻28 |
| 參考文獻 |
[1]G. E. Moore, “Cramming More Components onto Integrated Circuits”, Electronics 38 (1965) 56-59.
[2] S. Wolf, “Silicon Processing for the VLSI Era: The Submicron MOSFET” , vol. 3, Sunset, CA: Lattice, (1995).
[3] 莊達人編著，VLSI 製造技術，高立圖書有限公司 (1997).
[4] N. Li, X. Li, X. Yin, W. Wang, and S. Qiu, “Electroless Deposition of Open-End Cu Nanotube Arrays”, Solid State Commun. 132 (2004) 841-844.
[5] C. R., “Membrane-Based Synthesis of Nanomaterials”, Chem. Mater. 8 (1996) 1739.
[6] R. B. Wehrspohn, J. N. Chazalviel, and F. Ozanam, “Electrochemical Preparation of Porous Semiconductors: From Phenomenology to Understanding”, Mater. Sci. Eng. B 69 (2000) 1-10.
[7] C. T. Kresge, M. E. Leonowicz, W. J. Roth, J. C. Vartuli, and J. S. Beck, “Ordered Mesoporous Molecular Sieves Synthesized by a Liquid-Crystal Template Mechanism”, Nature 359 (1992) 710-712.
[8] G. E. Thompson, “Porous Anodic Alumina: Fabrication, Characterization and Applications”, Thin Solid Film 297 (1997) 192-201.
[9] A. P. Li, F. Muller, A. Birner, K. Nielsch, and U. G |
| 指導教授 |
鄭紹良(Shao-Liang Cheng)
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審核日期 |
2007-5-16 |
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