以規模經濟的觀點探討半導體晶圓廠產能規劃之研究:一個以系統模擬為基礎的方法

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姓名

呂麗香(Li-Hsiang Lu) 查詢紙本館藏

畢業系所

企業管理學系

論文名稱

以規模經濟的觀點探討半導體晶圓廠產能規劃之研究:一個以系統模擬為基礎的方法

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至系統瀏覽論文 ( 永不開放)

摘要(中)

晶圓廠的生產設備在五到七年會因製程演進而折舊淘汰，此外半導體廠商的產能大小會影響其供貨速度，如果產能不足，將嚴重影響相關電子產品的生產與供應速度，電子產品的生命週期短，產品價格隨時間快速下滑，在龐大的投資成本與景氣波動明顯下，正確的機台組合與快速的供貨能力，可以提升資本的使用效率，增強企業的競爭力。
本研究提出一套完整的半導體最佳產出決策，在考慮產品需求與機台組合的變動，來讓在製時間(cycle time)減到最小，讓產出保持在一個高水準，利用eM-plant模擬軟體構建實際半導體廠之生產系統，進行模擬實驗，產生出生產績效指標(在製時間)的模擬資料，再藉由實驗設計（DOE）的方法，將影響生產績效指標的各個機台區列為實驗控制因子，設計成每因子各兩個水準的一個單一重複的2k-5設計來分析因子影響效應，並透過統計方法尋找最適因子組合，來達到生產績效指標(在製時間)最小化之目的，最後以經濟學領域中的規模經濟與不經濟理論，找出最適規模的產能。

摘要(英)

The production equipment of semiconductor industry need to depreciation and elimination about 5 to 7 years because of the evolution of technology. Moreover the capacity of manufacturer will effect its delivery time. If throughput are shortage it will critically affect the production and supply speed of related electronic products. The life cycle of electronic products is short, wafer prices rapid reduce by time. With the astronomical capacity cots and high demand volatility, exact tool combination and rapid delivery time ability can make best use of capital and strength the competition of enterprise.
The thesis addresses a total solution to make best decision for semiconductor manufactory. Considering customer demand and variation tool sets to minimize the cycle time and keep throughout at a high level. By using eM-plant simulation tool to construct a real semiconductor manufacturing system, and obtain the data of cycle time. The tool sets that significantly influence production cycle time were identified through factor screening experiments. A 2k-5 un-replicate factional factorial design was performed. Base on the results from the factor screening experiments, using statistical analysis to find the best factor combination to reach minimize the cycle time. Finally, the optimal scale through the economies of scale and diseconomies of scale in economic field can find.

關鍵字(中)

★ 在製時間
★ 實驗設計

關鍵字(英)

★ cycle time
★ DOE

論文目次

中文摘要 I
ABSTRACT II
目錄 III
圖目錄 V
表目錄 VI
第一章緒論 1
1.1 研究動機 1
1.2 研究目的 1
1.3 論文架構 2
第二章半導體產業的特性及其管理問題分析 4
2.1 半導體產業的特性 4
2.2 半導體產業價值鏈介紹 7
2.3 半導體生產系統的特性 8
2.4 半導體產業管理問題分析 9
第三章理論及文獻回顧 12
3.1 各種產出決策模式介紹 12
3.1.1 數學規劃模式 12
3.1.2 等候網路模式 13
3.1.3 模擬模式 14
3.1.4 實驗設計 14
3.1.5. 規模經濟和不經濟 16
3.2 綜合論述 17
第四章決策模式的發展 18
4.1 問題的描述與分析 18
4.2 最佳產能決策流程圖 19
4.2.1. 起始解的建構 21
4.2.2. 部份因子實驗設計 22
4.2.3. 產能決策 24
第五章實例驗證 26
5.1 環境設定 26
5.2 半導體產業最佳產能決策範例 28
5.2.1 各工作區起始機台數與生產績效 28
5.2.2 實驗設計 29
5.2.3 決定各個顯著工作區應調整的機台數量 36
第六章結論與建議 44
6.1 結論 44
6.2 未來研究方向 45
REFERENCES 46
附錄 A: 產品途程 48
附錄B: 各情境模擬輸出 51
附錄 C: 210-5解析度為Ⅳ的部分因子設計的別名關係 57
附錄 D: TWO-SAMPLE T FOR CYCLE TIME 59

參考文獻

余業鑫(2003)，以生產力為觀點的半導體晶圓廠產能規劃方法，碩士論文，工業工程與工程管理，新竹。
Aybar, M., Potti, K., & LeBaron, T. (2002). Using simulation to understanding capacity constraints and improve efficiency on process tools. Proceedings of the 2002 Winter Simulation Conference, 1431-1435.
Bard, J. F., Srinivasan, K., & Tirupati, D. (1999). An optimization approach to capacity expansion in semiconductor manufacturing facilities. International Journal of Production Research, 37(15), 3359-3382.
Bermon, S., & Hood, S.J. (1999). Capacity optimization planning system (CAPS). Interfaces, 29(5), 31-51.
Bretthauer, K. M. (1995). Capacity planning in networks of queues with manufacturing application. Mathl. Comput. Modeling, 21(12), 35-46.
Chou, W., & Everton, J. (1996). Capacity planning for development wafer fab expansion. IEEE/Advanced Semiconductor Manufacturing Conference and Workshop, 17-22.
Chou, Y. C., & Hong, L. H. (2000). A methodology for product mix planning in semiconductor foundry manufacturing. IEEE Transactions on Semiconductor Manufacturing, 13(3), 278-285.
Dengiz, B., Bektas T., & Ultanir A. E. (2006). Simulation optimization based DSS application: A diamond tool production line in industry. Simulation Modeling Practice and Theory, 14(3), 296-312.
Iwata, Y., Taji, K., & Tamura, H. (2003). Multi-objective capacity planning for agile semiconductor manufacturing. Production Planning and Control, 14(3), 244-254.
Laure, W. (1999). Cycle time and bottleneck analysis. IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 42-47.
Martin, D. P. (1999a). Capacity and cycle time-throughput understanding system (CAC-TUS): An analysis tool to determine the components of capacity and cycle time in a semiconductor manufacturing line. IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 127-131.
Martin, D. P. (1999b). Total operational efficiency (TOE): The determination of 2 capacity and cycle time components and their relationship to productivity improvements in a semiconductor manufacturing line. IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 37-41.
Martin, D. P. (2000). Maximizing productivity improvements using short cycle time manufacturing (SCM) concepts in a semiconductor manufacturing line. IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 63-67.
Meyersdorf, D., & Yang, T. (1997). Cycle time reduction for semiconductor wafer fabrication facilities. IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 418-423
Montgomery, D. C. (2001). Design and analysis of experiments. New York: Wiley.
Nazzal, D., Mollaghasemi, M., & Anderson, D. (2005). A simulation-based evaluation of the cost of cycle time reduction in Agere Systems wafer fabrication facility-a case study. International Journal of Production Economics, 100(2), 300-313.
Nemoto, K., Akcali, E., & Uzsoy, R. M. (2000). Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication. IEEE Transactions on Electronics Packaging Manufacturing, 23(1), 39-47.
Ozawa, K., Wada, H., & Yamaguchi, T. (1999). Optimum tool planning using the x-factor theory. Proceedings of the 1999 IEEE International Symposium on Semiconductor Manufacturing (ISSM), 49-52.
Pindyck, R. S., & Rubinfeld, D. L. (2001). Microeconomics New Jersey: Pearson Prentice Hall.
Schömig, A. K. (2000). OR probleme in der mikrochipproduktion. Symposium on Operation Research, Dresden.
Stevenson, W. J. (1999). Production/operations management. Boston: Irwin.
Uzsoy, R., Lee, C. Y., & Martin-Vega, L. A. (1992). A review of production planning and scheduling models in the semiconductor industry. Part I: System characteristics, performance evaluation and production planning. IIE Transactions, 24(4), 47-60.
Wu, S. D., Erkoc, M., & Karabuk, S. (2005). Managing capacity in the high-tech industry: A review of literature. The Engineering Economist, 50(2), 125-158.

指導教授

呂俊德(Jun-Der Leu)

審核日期

2006-7-4

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