||In order to verify whether wafer can be able to achieve expected specification, generally every die will be probed completely after being fabricated in wafer fab. By such operation, we can use the essential index to improve wafer foundry’s quality and also the yield of wafers. In the mean time, IC design house hopes to get better yield during wafer probing process, normally they will try to ‘re-test’low-yield-wafer, no matter re-test entire gross dies or particular defective dies.|
In general, defective dies are classified by using different bin numbers; the bin numbers represent particular testing result or its performance. During failure analysis after finishing wafer testing, testing engineer can decide to re-test abnormal wafer directly if it’s out of yield limit set previously. As normally engineers just ‘hope’ to get higher yield recovered from second testing, they seldom know how to predict yield variation and regard the related profit before making decision of re-testing
Hence, this thesis attempts to propose a workable solution for wafer testing process by using Artificial Neural Back Propagation Network (BPN). Through a real example from CMOS Image Sensor probing process, it was presented to demonstrate the methodology. We finally hope to get the proper threshold for re-testing and also bring different opinion to the CMOS Image Sensor Company.
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