博碩士論文 93521012 詳細資訊




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姓名 洪煜凱(Yu-Kai Hung)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 微波存取全球互通頻段鏡像消除低雜訊放大器之研製及平衡式電路量測技術之研究
(Study on WiMax Image Rejection Low Noise Amplifier and Related Balanced Circuits Measurement Techniques)
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摘要(中) 本論文採用台積電0.35微米矽鍺雙載子互補金屬氧化半導體製程,實現微波存取全球互通頻段之平衡式射頻前端電路;論文內容分成平衡式電路量測技術與電路設計兩部分,其中第二章為平衡式電路量測技術之探討,主要介紹混合模態散射參數,並介紹對平衡式電路進行線性度以及雜訊指數之量測。第二部分的射頻前端電路設計以平衡式鏡像消除低雜訊放大器為主要研究內容。
本論文分析了數種鏡像消除式notch濾波器,提出了兩個差動式notch濾波器電路,分別為二階以及三階notch濾波器,經實作驗證後,與理論推測相同。並實作出了單端轉差動式以及全差動式鏡像消除放大器,分別驗證了被動式二階notch濾波器,以及所提出的差動式主動三階notch濾波器的功能。
以下概述各電路之實際量測結果:
第3-2節為單端轉差動式可變增益低雜訊放大器設計,其量測結果在高增益模式下,單端轉差模增益為11.6 dB,輸入1-dB壓縮點為-27.5 dBm,輸入三階截取點為-9 dBm,雜訊指數為4.89 dB,輸出埠功率差為5 dB,鏡像拒斥比為14.9 dB。量測結果在低增益模式下,單端轉差模增益為6.55 dB,輸入1-dB壓縮點為-23.5 dBm,輸入三階截取點為-10 dBm,雜訊指數為7.33 dB,輸出埠功率差為5.8 dB,鏡像拒斥比為11.5 dB。
第3-3節為差動式二階以及差動式三階notch濾波器 。差動式二階notch濾波器,其量測結果為零點可調頻率範圍2.72 GHz ~ 3.4 GHz,最低阻抗可達0.2歐姆。差動式三階notch濾波器,其量測結果為零點可調頻率範圍2.76 GHz ~ 3.4 GHz,最低阻抗可達0.74歐姆。極點可調頻率範圍3.3 GHz ~ 3.94 GHz,最高阻抗可達100歐姆。
第3-4節為差動式可變增益低雜訊放大器,其量測結果,在高增益模式下,差模增益為9.5 dB,輸入1dB壓縮點為-21 dBm,輸入三階截取點為-5 dBm,雜訊指數為8.12 dB,鏡像拒斥比為50.3 dB。在低增益模式下,量測結果為,差模增益為-4 dB,輸入1dB壓縮點為-19 dBm,輸入三階截取點為-3.5 dBm,雜訊指數為20.48 dB,鏡像拒斥比為34.7 dB。
摘要(英) In this thesis, RF front-end circuit for WiMax system is implemented by using tsmc SiGe 0.35?m BiCMOS process. This thesis is divided into two parts which are the study on balanced circuit measurement techniques and RF front-end circuits design. The first part is described in chapter 2, mixed-mode S-parameter, the linearity and noise figure measurement of balanced circuits are introduced.
The second part of RF front-end circuit for WiMax system is the main research in this thesis, such as balanced type image rejection low noise amplifier.
Several Image Rejection notch filter was analyzed and two differential notch filter using the second order and third order topology were proposed in this thesis. The implantation of the proposed filter shows the same performance with the simulation results. On the other hand, single to differential image-rejection LNA and fully differential image-rejection LNA were also presented. The theory of the passive second order notch filter and proposed differential active third order notch filter is also verified, respectively.
Following are the measured results of these designs.
Chapter 3-2 is single to differential image-rejection low noise amplifier design .In high gain operating mode, the measurements of single to differential gain is 11.6 dB, input power at the 1-dB gain compression point is -27.5 dBm, input third-order intercept point is -9 dBm., noise figure is 4.89 dB, output port power magnitude difference is 5 dB, image-rejection ratio is 14.9 dB. In low gain operating mode, the measurements of single to differential gain is 6.55 dB, input power at the 1-dB gain compression point is -23.5 dBm, input third-order intercept point is -10 dBm, noise figure is 7.33 dB, output port power magnitude difference is 5.8 dB, image-rejection ratio are 11.5 dB.
Chapter 3-3 are the differential second order and third order notch filter design. For differential second order notch filter, the measurement of zero tuning range is from 2.72 GHz to 3.4 GHz., and the minimum impedance can be low as 0.2 Ohm. For differential third order notch filter, the measurement of zero tuning range is from 2.76 GHz to 3.4 GHz, and the minimum impedance could be low as 0.2 Ohm.. The pole tuning range is from 3.3 GHz to 3.94 GHz, and the maximum impedance can be 100 Ohm.
Chapter 3-4 is the differential image-rejection low noise amplifier design. In high gain operating mode, the measurements of differential mode gain is 9.5 dB, input power at the 1 dB gain compression point is -21 dBm, input third-order intercept point is -5 dBm., noise figure is 8.12 dB, image-rejection ratio are 50.3 dB. In low gain operating mode, the measurements of differential mode gain is -4 dB, input power at the 1-dB gain compression point is -19 dBm, input third-order intercept point is -3.5 dBm, noise figure is 20.48 dB, image-rejection ratio is 34.7 dB.
關鍵字(中) ★ 鏡像消除式濾波器
★ 鏡像消除式低雜訊放大器
★ 平衡式電路量測技術
關鍵字(英) ★ balanced circuit measurement techniques
★ image rejection notch filter
★ image rejection LNA
論文目次 摘要 I
致謝 V
目錄 VI
圖目錄 VIII
表目錄 XII
第一章 緒論 1
1-1 研究動機 1
1-2 研究成果 1
1-3 章節簡述 1
第二章 平衡式電路量測技術 2
2-1 單端轉雙端放大器(三埠)之量測方法 2
2-1-1 三埠混合模態S參數 2
2-1-2 線性度量測 8
2-1-3 雜訊指數之量測方法 9
2-2差動式放大器(四埠)之量測方法 12
2-2-1 四埠混合模態S參數 12
2-2-2 線性度量測 19
2-2-3 雜訊指數之量測方法 19
第三章 平衡式鏡像消除低雜訊放大器 22
3-1鏡像消除濾波器之簡介 22
3-1-1 被動式二階鏡像消除濾波器 22
3-1-2 被動式三階鏡像消除濾波器 23
3-1-3 主動式二階鏡像消除濾波器 25
3-1-4 主動式三階鏡像消除濾波器 28
3-2 單端轉差動式(三埠)可變增益鏡像消除放大器 31
3-2-1 設計原理及目的 31
3-2-2 量測結果與分析 33
3-3 新型差動式notch 濾波器 40
3-3-1 設計原理及目的 40
3-3-2 量測結果與分析 43
3-4 差動式(四埠)可變增益鏡像消除放大器 51
3-4-1 設計原理及目的 51
3-4-2 量測結果與分析 53
第四章 結論與未來方向 65
4-1 結論 65
4-2 未來方向 65
參考文獻 66
參考文獻 [1]Anritsu Company, “Three and four port S-parameters: calibrations and mixed mode parameters,” Anritsu Application Note, 2001.
[2]D. E. Bockelman, and W. R. Eisenstadt, “Combined differential and common mode scattering parameter: Theory and simulation,” IEEE Transactions on Microwave Theory and Techniques, vol. 43, no 7, pp. 1530 –1539, July 1995.
[3]D. E. Bockelman, and W. R. Eisenstadt, “Pure-mode network analyzer for on-wafer measurements of mixed-mode S-parameters of differential circuits,” IEEE Transactions on Microwave Theory and Techniques, vol. 45, no 7, pp. 1071 - 1077, July 1997.
[4]D. E. Bockelman, W. R. Eisenstadt, and R. Stengel, “Accuracy estimation of mixed-mode scattering parameter measurements,” IEEE Transactions on Microwave Theory and Techniques, vol 47, no 1, pp. 102 – 105, Jan. 1999.
[5]F. Sanpietro, A. Ferrero, U. Pisani, and L. Brunetti, “Accuracy of a multiport network analyzer,” IEEE Transactions on Instrumentation and Measurement, vol 44, no 2, pp. 304 – 307, Apr 1995.
[6]A. Ferrero, F. Sampietro, and U. Pisani, “Multiport vector network analyzer calibration: a general formulation,” IEEE Transactions on Microwave Theory and Techniques, vol 42, no 12, pp. 2455 – 2461, Dec 1994.
[7]A. Ferrero, U. Pisani, and K.J. Kerwin, “A new implementation of a multiport automatic network analyzer,” IEEE Transactions on Microwave Theory and Techniques, vol 40, no. 11, pp. 2078 – 2085, Nov. 1992.
[8]D. E. Bockelman, and W. R. Eisenstadt, “ Combined differential and common-mode analysis of power splitters and combiners,” IEEE Transactions on Microwave Theory and Techniques, vol. 43, no 11, pp. 2627 – 2632, Nov. 1995.
[9]A. A. Abidi, and J. C. Leete, “De-embedding the noise figure of differential amplifiers,” IEEE Journal of Solid-State Circuits, vol. 34, no 6, pp. 882 – 885, June 1999.
[10]H. T. Ahn, and D. J. Allstot, “A 0.5-8.5 GHz fully differential CMOS distributed amplifier,” IEEE Journal of Solid-State Circuits, vol. 37, no 8, pp. 985 – 993, Aug 2002.
[11]A. A. Moneim Youssef, K. Sharaf, H.F. Ragaie, and M. Marzouk Ibrahim,” VLSI design of CMOS image-reject LNA for 950-MHz wireless receivers,” IEEE International Conference on Circuits and Systems for Communications, pp. 330 – 333 June 2002.
[12]J. A. Macedo, and M.A. Copeland, “ A 1.9-GHz silicon receiver with monolithic image filtering,” IEEE Journal of Solid-State Circuits, vol 33, no 3, pp. 378 –386, March 1998.
[13]T. K. Nguyen, S. K. Han, S. G. Lee,” Ultra-low-power 2.4 GHz image-rejection low-noise amplifier,” Electronics Letters, vol 41, no 15, pp. 842 – 843,July 2005.
[14]T. K. Nguyen, N. J. Oh, C. Y. Cha, Y. H. Oh, G. J. Ihm, and S. G. Lee, “ Image-rejection CMOS low-noise amplifier design optimization techniques,” IEEE Transactions on Microwave Theory and Techniques, vol 53, no 2, pp. 538 – 547, Feb 2005.
[15]H. Samavati, H. R. Rategh, and T. H. Lee, “A 5-GHz CMOS Wireless LAN Receiver Front End,” IEEE J. Solid-state Circuits, vol. 35, no. 5, pp. 765-771, May 2000.
[16]J.W.M Rogers, and C Plett, “A 5 GHz Radio Front-End with Automatically Q Tuned Notch Filter,” in IEEE Proc. Bipolar/BiCMOS Circuits and Technologv Meeting, pp. 69-72, Oct. 2002.
[17]M. A. Copeland, S. P. Voinigescu, D. Marchesan, P. Popescu, and M. C. Malerpard, “5-GHz SiGe HBT Monolithic Radio Transceiver with Tunable Filtering,” IEEE Trans. Microwave Theory and Tech., vol. 48, no. 2, pp. 170-180, Feb. 2000.
[18]M.A. Margarit, D. Shih, P.J. Sullivan, and F. Ortega, “A 5-GHz BiCMOS RFIC Front-End for IEEE 802.11d HiperLNA Wireless LNA,” IEEE J. Solid State Circuit, vol. 38, no. 7, pp. 1284-1287, July 2003.
[19]E. Ragonese, A. Italia, and G. Palmisano,” A 5-GHz Monolithic Silicon Bipolar Down-converter with On-chip ImageFiltering,” IEEE MELECON 2004, May 12-15, 2004, Dubrovnik, Croatia
[20] J. R. Long, “A Low-Voltage 5.1-5.8 GHz Image-Reject Downconverter RF IC,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1320-1328, Sept. 2000. J. P.
[21]Maligeorgos, and J. R. Long, “A Low-Voltage 5.1-5.8-GHz Image-Reject Receiver with Wide Dynamic Range,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1917-1925, Dec. 2000.
[22]C. W. Kim, and S. G. Lee,” A 5.25-GHz Image Rejection RF Front-End Receiver With Polyphase Filters,” IEEE Microwave and Wireless Components Letters, vol. 16, no. 5, MAY 2006.
[23]R.A. Baki, and N. El-Gamal,” A 1.5V multigigahertz CMOS tunable image reject notch filter,” The 14th International Conference on Microelectronics, pp. 144 – 147, Dec. 2002.
[24]M. Rajashekharaiah, P. Upadhyaya, H. Deukhyoun, and E. Chen, “A new gain controllable on-chip active balun for 5 GHz direct conversion receiver,” IEEE International Symposium on Circuits and Systems, 2005. pp. 5115 – 5118, vol. 5, May 2005.
[25] M. K. Rajashekharaiah, T. T. C. Boon, K. N. Kumar, S. J. Wong, “A fully integrated variable gain 5.75-GHz LNA with on chip active balun for WLAN,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 439- 442, June. 2003.
指導教授 邱煥凱(Hwann-Kaeo Chiou) 審核日期 2006-7-19
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