博碩士論文 93521016 詳細資訊




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姓名 黃佳淳(Jia-Chun Huang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於數位視頻廣播系統中之自動增益放大器 及接受端濾波器設計
(Automatic Gain Control and Continuous-Time Receive Filter in DVB-T/H Receiver Design )
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摘要(中) 在本論文中,描述一個類比前端電路,主要是以基頻接收端通訊系統應用為目標,應用在數位視頻廣播系統中。內包含一個經由數位控制的自動增益放大器和一個抗混淆濾波器。在接收端的信號路徑上包含一個可程式化增益放大器,這個類比的放大器擁有51dB 的動態增益範圍,並且由一階的數位控制迴路來自動調整其增益量。使其輸出可到達160mVpp。在輸入震幅也是160mVpp 的情況下,經由
雙端輸入模擬出的全諧波失真(THD)小於 -60dB。此設計已使用台灣積體電路公司所提供 0.18 微米 CMOS 製程製作。操作在1.8V 電壓下,消耗功率為13 毫瓦。緊接著這個自動增益放大器是一個頻寬為4MHz 的五階Chebyshev 低通濾波器,此外一個運算跨導放大器(OTA)將被運用在這個濾波器中。輸入震幅為160mVpp模擬出的全諧波失真(THD)小於 -60dB。操作電壓在1.8V,此電路將被驗證在佈局後(post-layout)的模擬上。
摘要(英) This paper describes a digitally controlled automatic gain control (AGC) and anti-aliasing
filter subsystems for the analog front-end (AFE), in which it can be used to support the digital video broadcasting in DZIF (double conversion with zero second IF) architecture. The receiving path contains a programmable-gain amplifier (PGA) with the self-tuning gain circuit. The dynamic range of the PGA, which is controlled by a digital loop to form a first order system, is 51dB. The third-harmonic distortion is less than -60dB for differential input signal up to 160mVpp. This chip has already been fabricated in a TSMC 0.18μm standard CMOS technology while the supply voltage is 1.8V and its power consumption is 13mW. Following the proposed AGC, a 4-MHz fifth-order Chebyshev low-pass Gm-C filter is also described in detail. In addition, an operational transconductance amplifier (OTA) with an additional enhanced amplifier structure is utilized to perform the voltageto-current conversion. The THD is less than -60dB over the input range of 160mVpp and the supply voltage is 1.8V. This proposed filter has also been completely verified by the post-layout simulation.
關鍵字(中) ★ 濾波器
★ 自動增益放大器
★ 數位視頻廣播系統
關鍵字(英) ★ DVB-T/H
★ AGC
★ Filter
論文目次 Abstract iv
Acknowledgments v
List of Tables ix
List of Figures x
Chapter 1 Introduction 1
1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 2 System Architectures and Design 4
2.1 Receiver Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.2 Low-IF Receiver Architecture . . . . . . . . . . . . . . . . . . . . . 5
2.1.3 Zero-IF Receiver Architecture . . . . . . . . . . . . . . . . . . . . . 8
2.1.4 Double Conversion Zero-IF Architecture with DVB-T/H . . . . . . 12
2.2 Receiver Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Signal Control Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1 Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.2 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Proposed Digital Feedback AGC . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.1 Gain Control Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.2 First Order Approximation Analysis . . . . . . . . . . . . . . . . . 19
2.5 Simulation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 3 Programmable-Gain Amplifier Design 23
3.1 Introduce PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Inverting and Noninverting Amplifier . . . . . . . . . . . . . . . . . . . . . 25
3.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.1 Current Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.2 Voltage Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3.3 Variable Input Resistors . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3.4 Common Mode Feedback . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3.5 Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 VLSI Implementation and Simulation Result . . . . . . . . . . . . . . . . . 35
3.4.1 Layout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 4 Anti-Aliasing Filter Design 41
4.1 Introduce OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2 Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.1 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.2 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3.1 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3.2 Operation Transconductance Amplifier . . . . . . . . . . . . . . . . 48
4.3.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 5 Conclusion and Future Works 51
5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Bibliography 53
參考文獻 [1] European Telecommunications Standards Inst. (ETSI), ETSI EN 302 304 V1.1.1
(2004-11): Digital Video Broadcasting (DVB); Transmission System for Handheld
Terminals (DVB-H), 2004.
[2] European Telecommunications Standards Inst. (ETSI), ETSI TR 101 190: Digital
Video Broadcasting (DVB); Implementation guidelines for DVB terrestrial services;
Transmission aspects.
[3] European Telecommunications Standards Inst. (ETSI), ETSI 300 744 (1997): Digital
Broadcasting Systems for Television, Sound and Data Services; Framing Structure,
Channel Coding and Modulation for Digital Terrestrial Television, 1997.
[4] Muh-Tian Shiue, Kuang-Hu Huang, Cheng-Chang Lu, Chorng-Kuang Wang, Winston
I. Way, ¡§A VLSI Design of Dual-Loop Automatic Gain Control for Dual-Mode
QAM/VSB CATV Modem,¡¨ Proc. IEEE Int. Symposium Circuits and Systems, Monterey,
CA, 1998.
[5] Jan Crols and Michiel S. J. Steyaert, ¡§Low-IF Topologies for High-Performance Analog
Front Ends of Fully Integrated Receivers,¡¨ IEEE Transactions on Circuits and
Systems¡VII: Analog and Digital Signal Processing, Vol. 45, no. 3, MARCH 1998.
[6] Behzad Razavi, RF Microelectronics. Prentice-Hall, 1997.
[7] Won Namgoong and Teresa H. Meng, ¡§Direct-Conversion RF Receiver Design,¡¨ IEEE
Transcation on Communications, Vol. 49, no. 3, MARCH 2001.
[8] Bengt Lindoff and Peter Malm, ¡§BER Performance Analysis of a Direct Conversion
Receiver,¡¨ IEEE Transcation on Communications, Vol. 50, no. 5, MAY 2002.
[9] Guanbin Xing, Manyuan Shen, and Hui Liu, ¡§Frequency Offset and I/Q Imbalance
Compensation for Direct-Conversion Receivers,¡¨ IEEE Transacation on Wireless
Communications, Vol. 4, no. 2, MARCH 2005.
[10] V. K. P. Ma and T. Ylamurto, ¡§Analysis of IQ imbalance on initial frequency offset
estimation in direct down-conversion receivers,¡¨ in Proc. IEEE 3rd Workshop Signal
Processing Advances in Wireless Communications (SPAWC), pp. 158V161, Taoyuan,
Taiwan, Mar. 2001.
[11] K. P. Pun, J. E. Franca, C. Azeredo-Leme, C. F. Chan, and C. S. Choy, ¡§Correction
of frequency-dependent I/Q mismatches in quadrature receivers,¡¨ Electron. Lett., vol.
37, pp. 1415V1417, Nov. 2001.
[12] J.K. Cavers, M.W. Liao, ¡§Adaptive compensation for imbalance and offset losses in
direct conversion transceivers,¡¨ IEEE Transactions on Vechicular Technology, vol. 42,
pp. 581-588, Nov. 1993.
[13] M. Valkama, M. Renfors, V. Koivunen, ¡§Advanced methods for I/Q imbalance compensation
in communication receivers,¡¨ IEEE Transactions on Signal Process, vol. 49,
pp. 2335-2344 , Oct. 2001.
[14] Hsing-Hung Chen, Po-Chiun Huang, Chao-Kai Wen and Jiunn-Tsair Chen ¡§Adaptive
Compensation of Even-Order Distortion in Direct Conversion Receivers,¡¨ IEEE
Transactions on Vehicular Technology, vol.1, pp. 271 - 274, Oct. 2003.
[15] Mark Dawkins, Alison Payne Burdett, Nick Cowley ¡§A Single-Chip Tuner for DVBT,¡¨
IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp. 1307 - 1317, Aug. 2003.
[16] H. Darabi and A. Abidi, ¡§A 4.5-mW 900-MHz CMOS receiver for wireless paging,¡¨
IEEE J. Solid-State Circuits, vol. 35, pp. 1085V1096, Aug. 2000.
[17] Olujide A. Adeniran, Andreas Demosthenous, Chris Clifton, Sam Atungsiri, Randeep
Soin, ¡§A CMOS Low-Power ADC for DVB-T and DVB-H Systems,¡¨ IEEE International
Symposium on Circuits and Systems, vol. 1, pp. 209 - 212, May 2004.
[18] Patrick Antoine, Philippe Bauser, Hugues Beaulaton, Martin Buchholz, Declan
Carey, Thierry Cassagnes, T. K. Chan, Stephane Colomines, Fionn Hurley, David
T. Jobling, Niall Kearney, Aidan C. Murphy, James Rock, Didier Salle, and Cao-
Thong Tu, ¡§A Direct-Conversion Receiver for DVB-H,¡¨ IEEE Journal of Solid-State
Circuits, vol. 40, no. 12, pp. 2536 - 2546 December 2005.
[19] H. Meyr, G. Ascheid, Digital Communication Receivers, Phase-, Frequency-Locked
Loops, and Amplitude Control (Wiley Series in Telecommunications and Signal Processing)
John Wiley & Sons, 1990.
[20] Cheng-Chang Lu, Digitized CMOS ModulatorBAGC and Carrier Recovery for
QAM/VSB Transceiver, Master Thesis, National Central University, 1995.
[21] Hao-Shun Chang, Automatic Gain Control for VDSL Receiver Analog Front End,
Master Thesis, National Taiwan University, 2000.
[22] C. Richard Johnson, William A. Sethares, ¡§Telecommunications Breakdown: Concepts
of Communication Transmitted via Software-Defined Radio,¡¨ Pearson Prentice
Hall, 2003.
[23] R. Harjani, ¡§A Low-Power CMOS VGA for 50 Mb/s Disk Drive Read Channels¡¨,
IEEE Trans. Circuits Syst. II, vol. 42, pp. 370V376, June 1995.
[24] C.C. Hsu, J.T. Wu, ¡¨A Highly Linear 125-MHz CMOS Switched Resistor Programmable
Gain Amplifier,¡¨ IEEE Journal of Solid State Circuits, vol. 38, no. 10,
pp. 1663-1670, Oct. 2003.
[25] Behzad Razavi, Design of Analog CMOS Integrated Circuits. Mc Graw Hill, 2001.
[26] Shan-Chih Tsou, CMOS Variable Gain Amplifier for Multi-Standard Receiver. Master
Thesis, National Tsing Hua University, 2004.
[27] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, Analysis and
Design of Analog Integrated Circuits. John Wiley and Sons Inc., 2001.
[28] David A. Johns and Ken Martin, Analog Integrated Circuit Design. John Wiley and
Sons Inc., 1997.
[29] A. L. Coban and P. E. Allen, ¡¨Low-voltage CMOS transconductance cell based on
parallel operation of triode and saturation transconductors,¡¨ Electron. Lett., vol. 30,
no. 14, pp. 1124V1126, 1994.
[30] E. S. Sinencio and J. S. Martinez, ¡§CMOS transconductance amplifiers, architectures
and active filters: A tutorial,¡¨ in IEE Proc. Circuits Devices Syst., vol. 147, pp. 3V12,
Feb. 2000.
[31] Intersil AN9718. ¡§Analog Amp Linearity Characterization via Probability Weighted
Multitone Power Ratio Testing,¡¨ Application Note, 1997.
[32] Rolf Schaumann, Mac E. Van Valkenburg, Design of Analog Filters. Oxforf University
Press, 2001.
[33] Sung-Hyun Yang, Kyu-Ho Kim, Yong-Hwan Kim, Younggap You, and Kyoung-Rok
Cho, ¡§A Novel CMOS Operational Transconductance Amplifier Based on a Mobility
Compensation Technique,¡¨ IEEE Transactions on Circuits and Systems¡VII: Express
Briefs, Vol. 52, no. 1, pp. 37 - 42, Jan. 2005.
[34] Tae Wook Kim and Bonkee Kim, ¡§A 13-dB IIP3 improved low-power CMOS RF programmable
gain amplifier using differential circuit transconductance linearization for
various terrestrial mobile D-TV applications,¡¨ IEEE Journal of Solid State Circuits,
vol. 41, no. 4, pp. 945-953, Apr. 2006.
[35] Chua-Chin Wang, Ching-Li Lee, Li-Ping Lin, Yih-Long Tseng, ¡§Wideband 70dB
CMOS digital variable gain amplifier design for DVB-T receiver¡¦s AGC,¡¨ IEEE International
Symposium on Circuits and Systems, vol. 1, pp. 356 - 359, May 2005.
[36] Sanz A.T., Cehna S., Calvo B., ¡§High linear digitally programmable gain amplifier,¡¨
IEEE International Symposium on Circuits and Systems, vol. 1, pp. 280 - 211, May
2005.
指導教授 薛木添(Muh-Tian Shiue) 審核日期 2006-7-20
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