用於多核心/裸晶系統晶片之有效測試與良率提升技術

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黃瑜真(YU-JEN HUANG) 查詢紙本館藏

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電機工程學系

論文名稱

用於多核心/裸晶系統晶片之有效測試與良率提升技術
(Efficient Test and Yield-Enhancement Techniques for Multi-Core/Die System Chips)

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★ 用於修復嵌入式記憶體之基礎矽智產	★ 自我修復記憶體之備份分析評估與驗證平台
★ 使用雙倍疊乘累加命中線之低功率三元內容定址記憶體設計	★ 可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計
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摘要(中)

使用矽穿孔(through-silicon-via, TSV)作為垂直連接多層二維裸晶的三維技術是目前新興的積體電路設計技術之一。此技術可帶來許多優於二維積體電路設計技術的優點。然而，此技術目前存在許多挑戰，包含設計、製造、測試、良率等。這些挑戰在三維積體電路可量產前都須一一克服。其中，測試與良率為最關鍵的問題與挑戰。因此，對於三維晶片而言，有效的測試與良率提升技術是非常重要的。
三維晶片包含了數個二維晶片，其中二維晶片可能以多核心(multi-core)架構設計而成。無論是多核心裸晶或是多核心晶片，記憶體皆占了相當大的面積比例。因此在本論文第一部分，我們提出兩種測試多核心晶片中小記憶體的方法，稱為加強型IEEE 1500 測試封套(IEEE standard 1500 wrapper-based)測試方法及可擴充與低成本內建自我測試(scalable and low-cost built-in-self-test, BIST)電路方法。加強型IEEE 1500 測試封套測試技術利用既有的IEEE 1500 測試封套來測試已接到IEEE 1500 測試封套的記憶體。實驗結果顯示，此方法所付出的額外面積相當小，對於一個90nm 製程64K-bit 大小的單埠記憶體(single-port RAM)只需要0.58%，對於64K-bit 的多埠記憶體(multi-port RAMs)只要0.57%。用於記憶體陣列的可擴充與低成本內建自我測試電路可降低面積消耗與增加可擴充性，但不造成過長的測試時間。此外，我們提出錯誤定位的方法來識別錯誤字組中錯誤位元的位置。實驗結果顯示，此方法對於16個64K-bit 的記憶體只需0.89%的額外面積消耗。我們亦實現此電路於測試晶片中，用來測試九個記憶體。
明顯地，在三維晶片中，矽穿孔的測試與良率相當重要。為了偵測與容忍錯誤的矽穿孔，我們在本論文的第二部分提出內建自我修復電路(built-in self-repair, BISR)來測試與修復三維晶片中的矽穿孔。此內建自我修復電路藉由矽穿孔排列成類似於記憶體的陣列形式，來提供較高的修復能力與良率。此外，我們亦提出廣域式(global)的修復資訊儲存方法來降低晶片中所需保險絲(fuse)的使用量。模擬與分析結果顯示出，與既有的矽穿孔修復架構以及達到相同的整體良率結果相比，所提出之內建自我修復電路可以大幅降低額外的面積消耗與測試時間。例如，對於有512 個矽穿孔的三維寬輸出入(wide-IO) DRAM，此內建自我修復技術可以降低32.4%的額外面積消耗與73.4%的測試時間。
論文的第三部分，我們討論了更複雜的矽穿孔錯誤模型(fault model) ─ 串音錯誤(crosstalk faults)。我們針對不同型態的矽穿孔串音錯誤提出不同的測試演算法。接著，我們提出內建自我測試電路與測試封套測試架構來實現測試演法。實驗結果顯示，對於一個32x16 大小的矽穿孔陣列與9T 串音錯誤模型，使用0.18μm製程實現的內建自我測試電路的額外面積消耗為28.1%。此矽穿孔的大小為15x15μm2。然而，對於整體面積為25mm2 的三維晶片而言，此額外面積消耗僅為1.86%。對於同樣的矽穿孔陣列，所提出的測試封套測試架構的額外面積消耗為60.6%。相較於一般需要兩個儲存元件的測試封套測試架構的額外面積消耗為73.92%而言，可節省18%的面積比例。
從應用面來看，堆疊記憶體的多核心裸晶已被視為相當適用於三維晶片中的架構。如上述提及，三維晶片的良率是關鍵的問題。因此，我們針對同質性(homogeneous)多核心記憶體與處理器堆疊的三維晶片，提出提升良率的方法，稱為一階層(one-level)與二階層式(two-level)的重組(reconfigurable)方法。在記憶體晶片中，我們增加了水平方向的位移重組方法。在處理器晶片中，我們增加了垂直方向的位移重組方法。因此，記憶體與處理器皆可位移來盡可能組成最多的好的記憶體與處理器組。同時，我們也提出啟發式演算法(heuristic algorithm)來快速的計算記憶體與處理器晶片的可重組性。因此，三維多核心晶片的良率就可藉由我們提出的方法來提升良率。實驗結果顯示，此重組方法僅使用可忽略的額外面積消耗即可明顯地提升整體良率。例如，對於容許錯一個記憶體與處理器組的64 核心的三維晶片而言，與沒有使用任何提升良率方法的晶圓對晶圓堆疊三維晶片相比，所提出的一階層與二階層方法可提升1.71%與6.08%的整體良。

摘要(英)

Three-dimensional (3D) technology vertically integrating multiple 2D dies using the through-silicon-via (TSV) is one emerging integrated circuit design technology. It offers many advantages over the 2D integration technology. However, many challenges, such as the design, manufacturing, test, yield, and etc., should be overcome before the volume production of 3D ICs become possible. Among these challenges, test and yield are two key challenges. Effective test and yield-enhancement techniques are thus important for 3D ICs.
A 3D IC consists of multiple dies in which a die may be designed with multi-core architecture. Regardless of the multi-core die or the multi-die chip, memories usually dominate a large portion of the silicon area. In the first part of the thesis, therefore, we focus on the testing of RAMs in multi-core dies. Two low-area test schemes are proposed to test small RAMs, an enhanced IEEE 1500 wrapper-based test scheme and a scalable and low-cost built-in-self test (BIST) scheme. The enhanced IEEE 1500 wrapper-based test scheme utilizes existing IEEE standard 1500 wrappers to test RAMs connected to the IEEE 1500 wrappers. Experimental results show that the additional area cost for extending the IEEE 1500 wrapper to an enhanced one is small, which is only about 0.58% for a 64K-bit single-port RAM and only 0.57% for a 64K-bit two-port RAM in 90nm technology. The scalable and low-cost BIST scheme for an array of memories can reduce the area cost without incurring long testing time and increase the scalability. Furthermore, a fault-location approach is proposed to identify the positions of faulty bits in a faulty word. Simulation results show that the proposed BIST scheme has small area cost, e.g., the BIST circuit for 16 1024×64-bit RAMs only needs about 0.89%hardware overhead. A test chip is also implemented to demonstrate the proposed BIST scheme for 9 RAMs.
Clearly, the test and yield of TSV are very important for 3D ICs. To detect and tolerate defective TSVs, we propose a built-in self-repair (BISR) scheme to test and repair TSVs in 3D ICs in the second part of the thesis. The BISR scheme, arranging the TSVs into arrays similar to memories, can provide high repair yield. Furthermore, a global fusing methodology is proposed to reduce the requirement of fuses. Simulation and analysis results show that the proposed BISR scheme can drastically reduce the area cost and test time in comparison with an existing TSV repair scheme for the same final yield of TSVs under repair. For a 3D wide-IO DRAM with 512 TSVs, for example, the proposed repair scheme can achieve 32.4% area reduction and 73.4% test time reduction.
In the third part of the thesis, we discuss more complex fault models of TSVs — the crosstalk faults. Test algorithms for testing different types of crosstalk faults of TSVs are proposed. Then, a BIST architecture and the wrapper-based test architecture are proposed to realize the test algorithms for TSVs. Simulation results show that the area overhead of the proposed BIST circuit for a 32×16 TSV array with 9T crosstalk faults is 28.1% using 0.18μm CMOS technology, where each TSV cell size is 15 × 15μm2. However, the area overhead of the BIST circuit is only 1.86% to a 25mm2 die. The area overhead of the proposed wrapper-based test architecture is 60.6% for the same TSV array which can save 15% area overhead compared with the typical two-storage wrapper test architecture which has 73.92% area overhead to the TSV array.
In the application point of view, multi-core die stacked with memories has been considered as one good candidate for 3D ICs. As aforementioned, the yield is one critical issue for 3D ICs, therefore, we propose yield-enhancement techniques, one-level and two-level reconfiguration scheme, for homogeneous multi-core memory and processor stacked 3D ICs. For a memory and processor stacked 3D ICs, a horizontal shifting reconfiguration scheme is added in the memory die while a vertical shifting reconfiguration scheme is added in the processor die. Then memory and processor cores can be swapped which can make as many good memory-processor pairs as possible. Also, heuristic reconfiguration algorithms are developed to fast calculate the reconfigurability of the memory and processor dies. Then the yield of 3D multi-core ICs can be improved by the proposed yield enhancement techniques. Experimental results show that the proposed reconfiguration schemes can significantly increase the yield from 1% to 11% using negligible area overhead. For example, if the 3D IC is a 63-out-of-64 system, the proposed one-level and two-level reconfigurations schemes can increase 1.71% and 6.08% of final yield compared with randomly wafer-to-wafer stacking without any yield-enhancement technique.

關鍵字(中)

★ 矽穿孔
★ 記憶體測試
★ 記憶體診斷
★ 良率提升
★ 隨機存取記憶體
★ 系統晶片
★ 內建自我測試
★ 三維晶片
★ 內建自我修復
★ 多核心

關鍵字(英)

★ memory testing
★ yield-enhancement
★ diagnosis
★ random access memory (RAM)
★ System-on-Chip (SOC)
★ through-silicon-via (TSV)
★ built-in self-repair
★ built-in self-test
★ 3D IC
★ multi-core

論文目次

1 Introduction 1
1.1 3D Integration Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 TSV Techniques and Bonding Techniques . . . . . . . . . . . . . . . . . . 1
1.1.2 3D IC Architectures and Applications . . . . . . . . . . . . . . . . . . . . 3
1.1.3 Challenges of 3D ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Test and Yield-Enhancement Techniques for 2D Dies . . . . . . . . . . . . . . . . 6
1.2.1 2D System-on-Chips (SOCs) in a 3D IC . . . . . . . . . . . . . . . . . . . 6
1.2.2 Memory Built-In Self-Test Circuit . . . . . . . . . . . . . . . . . . . . . . 8
1.2.3 IEEE Standard 1500 Architecture . . . . . . . . . . . . . . . . . . . . . . 9
1.2.4 Existing Memory Built-In Self-Test Schemes . . . . . . . . . . . . . . . . 10
1.3 Test and Yield-Enhancement Techniques for 3D Dies . . . . . . . . . . . . . . . . 13
1.3.1 Defects in TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.2 Testing of 3D ICs and TSVs . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.3 Existing TSV Redundancy and Reconfiguration Schemes . . . . . . . . . . 16
1.4 Thesis Scope and Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2 Built-In Self-Test Techniques for Small RAMs in SOCs 22
2.1 Enhanced IEEE 1500 Test Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.1 Architecture of the Enhanced IEEE 1500 Test Wrapper . . . . . . . . . . . 23
2.1.2 Operations of the Proposed Enhanced 1500 Wrapper . . . . . . . . . . . . 25
2.1.3 Implementation of Wrapper Cell and Address Generator . . . . . . . . . . 27
2.1.4 Multi-Port RAM Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1.5 Test Time Reduction Techniques . . . . . . . . . . . . . . . . . . . . . . . 31
2.2 Pipelined BIST Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.1 BIST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2.2 BIST Sharability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.2.3 Test Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.2.4 BIST for an Array of Memories . . . . . . . . . . . . . . . . . . . . . . . 42
2.2.5 Support of Interconnection Test . . . . . . . . . . . . . . . . . . . . . . . 43
2.3 Memory Repair and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.3.1 Memory Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.3.2 Memory Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.3.3 BIST Modification for Memory Diagnosis . . . . . . . . . . . . . . . . . . 49
2.4 Simulation and Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.4.1 Design of the Enhanced IEEE 1500 wrapper . . . . . . . . . . . . . . . . 51
2.4.2 Analysis of the Enhanced IEEE 1500 wrapper . . . . . . . . . . . . . . . . 53
2.4.3 Design of the Pipelined BIST Circuit . . . . . . . . . . . . . . . . . . . . 59
2.4.4 Analysis of the Pipelined BIST Circuit . . . . . . . . . . . . . . . . . . . 63
2.4.5 Architecture of the Test Chip . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.4.6 Results of Wafer-level Test . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.4.7 Results of Post-bond Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3 Self-Test and Repair for TSVs in 3D ICs 73
3.1 Proposed Testing Scheme for TSV Arrays . . . . . . . . . . . . . . . . . . . . . . 74
3.1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.1.2 Test Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.1.3 KGS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.2 Simulation Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.2.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.2.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.2.3 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.3 Proposed TSV Redundancy and Reconfiguration Scheme . . . . . . . . . . . . . . 87
3.4 Proposed BISR Scheme for TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.4.1 Overview of the BISR scheme . . . . . . . . . . . . . . . . . . . . . . . . 92
3.4.2 BISR Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.4.3 BISR Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.5 Fusing Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.5.1 Connection of Repair Register and Fuse . . . . . . . . . . . . . . . . . . . 99
3.5.2 Design of Fuse Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.6 Analysis and Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.6.1 Hardware Cost Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.6.2 Fuse Cost Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.6.3 Yield Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.6.4 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4 Testing Crosstalk Faults of TSVs in 3D ICs 116
4.1 Fault Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.1.1 5-TSV and 9-TSV Fault Models . . . . . . . . . . . . . . . . . . . . . . . 118
4.1.2 Coupling Effects of TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.2 Proposed Test Algorithms for Crosstalk Faults of TSVs . . . . . . . . . . . . . . . 121
4.2.1 Parallel Test Algorithms and Wrapper-based Test Scheme . . . . . . . . . 121
4.2.2 Test Algorithms for 5T-XF using BIST Scheme . . . . . . . . . . . . . . . 125
4.2.3 Test Algorithms for 9T-XF using BIST Scheme . . . . . . . . . . . . . . . 126
4.3 Proposed Testing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.3.1 Proposed BIST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.3.2 Test Operation Flow of the BIST Scheme . . . . . . . . . . . . . . . . . . 132
4.4 Simulation Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.4.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.4.2 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5 Yield-Enhancement Techniques for Memory and Processor Stacked 3D ICs 141
5.1 Yield of Multi-Core 2D and 3D ICs . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.2 Yield-Enhancement Techniques for 3D ICs . . . . . . . . . . . . . . . . . . . . . 143
5.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.4 Proposed Yield Enhancement Techniques . . . . . . . . . . . . . . . . . . . . . . 145
5.4.1 Proposed Yield-Enhancement Flow . . . . . . . . . . . . . . . . . . . . . 145
5.4.2 Proposed One-level Reconfiguration Scheme . . . . . . . . . . . . . . . . 146
5.4.3 Proposed Two-level Reconfiguration Scheme . . . . . . . . . . . . . . . . 153
5.4.4 Wafer Matching Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.5 Simulation Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.5.1 Area Overhead and Yield Model . . . . . . . . . . . . . . . . . . . . . . . 159
5.5.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6 Conclusion and Future Work 169
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

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指導教授

李進福(Jin-Fu Li)

審核日期

2012-4-20

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