博碩士論文 93521032 詳細資訊




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姓名 黃啟書(Chi-shu Huang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 增強CMOS鎖相迴路可靠度
(Relaiblity Enhanment of CMOS PLL)
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摘要(中) 摘要
良率與可靠度是半導體產品的兩項重要因素,在製造過程中發生了一些外在情況而造成在製造過程中產生了一些缺陷,然而在CMOS IC中較為常見的是在MOS元件上閘氧化層上的問題,一般我們稱之為Defect (缺陷),這個原因在IC剛被製造出來時很難被發現的,直到過了一段時間才會因為這個缺陷使得閘氧化層損毀使得電路的執行效率大大地減低,因此要如何提早發覺並且將其避免類似的情況發生就有不少方法出現,而在目前較有效率的方式Burn-in(燒烤),這個方法就是將IC送進考箱裡利用高溫高壓的方示讓有缺陷的MOS電路提早損毀,如此一來便可以避免這些產品流入客戶的手中,但是這個方法不但提高了產品的成本也增加許多的測試時間。
還有另外的方式是使用傳統Iddq Test以及0-1 Test但是對於類比電路而言其實可能並不適用,因此我們採用另一種方式來測就是加高電壓的方式來對有缺陷的MOS加壓,再經我們的推導可以算出加壓的電壓與加壓時間為何,如此一來就可精確的判斷出沒有缺陷的MOS可以承受的時間為多長,而達不到這一時間的MOS則會損毀,這樣我們就可以不用花太多的時間與金錢來提高可靠度,因此我們選則PLL(Phase Clock Loop)作為本篇論文對類比電路採用加壓測試的電路,而PLL又可分為三種分別為線性鎖相迴路(Linear PLL)、數位式鎖相迴路(Digital PLL)以及全數位式鎖相迴路(ADPLL),其中線性鎖相迴路為完全的類比電路所組成,全數位式鎖相迴路則為整個電路均是以數位為架構所成的電路,而我們這一次PLL所選用的是數位式鎖相迴路,這一種PLL的特點是在相位頻率偵測器由原先的類比電路架構改為數位電路架構其於的部份則均為類比電路,因此我們選用這一種型式的PLL便可加以驗證加壓測試方式可以對類比電路或數位電路均適用。
摘要(英) Astract
Yield and reliability are two important factors of the semiconductor products, it produces some defects in the course of making to cause some external situations in the course of making, but comparatively a common one is that the floodgate on MOS component oxidizes one story of questions had in CMOS IC, generally we call that Defect (defect ), this reason is very difficult to be found when IC was just made out, can make floodgate oxidize one layer of damage make the execution efficiency of the circuit lower greatly by the defect until after a while, want how discover and prevent similar situation from is it have methods appear to take place it ahead of time, more efficient way Burn-in at present (roast), this method is to send IC to while testing the case and utilize the side of high-temperature high pressure to show and let defective MOS circuit be damaged ahead of time, can prevent these products from flowing into the customer’’s hands once coming so, but this method has not only raised the cost of the products also increases a lot of test time.
Other ways use traditional Iddq Test and 0-1 Test but but the speech may actually not be suitable for imitating the circuit, it is that a way with high voltage pressurize to defective MOS so we adopt another way to examine, and then by to is it can calculate voltage that pressurize and why it will be pressurization time to derive us, how long is the acceptable time of MOS without defect of very accurate judging so once coming, MOS not reaching this time will be damaged, in this way we needn’’t spend too much time and money raising the reliability , so we select PLL (Phase Clock Loop ) to adopt the circuit that pressurize and test in imitating the circuit as this page thesis, and it is linear phase locking return circuits respectively that PLL can be divided into three kinds (Linear PLL), several type phase locking return circuit (Digital PLL ) and location type phase locking return circuit (ADPLL ) totally, linear phase locking return circuit among them make up by complete simulation circuit, totally the location type phase locking return circuit regards digit as the circuit become of structure for the whole circuit, and we several type phase locking return circuit, this at phase place frequency detect examining device change it several circuit structure their from original simulation circuit structure to in kinds of the characteristics of PLL on part imitate by circuit, so PLL that we selected this kind of modelling for use can prove that it can be to imitating the circuit or the digit circuit suitably to pressurize to test the way .
關鍵字(中) ★ 鎖相迴路 關鍵字(英) ★ Relaiblity Enhanment
★ PLL
論文目次 Table of contents Page
Chapter1 INTRODUCTION 1
1.1 Motivation…………………………………………………… 2
1.2 Organization…………………………………………………. 3
Chapter2 BRACKGROUND 4
2.1 Physical Failure Mechanisms……………………………….. 4
2.2 Failure Mechanisms…………………………………………. 4
2.2.1 CMOS Gate-Oxide Reliability………………………………. 5
2.3 Defect Models……………………………………………...... 7
2.3.1 Hole-Induced (Reciprocal-Field) Breakdown Model……………………....................................................... 7
2.3.2 Thermochemical (Linear-Field) Breakdown Model………………………………………………………... 7
2.4 Extreme-Voltage Stress Tests………………………………... 8
2.5 Burn-in…….………………………………………………… 10
2.6 Extreme-Voltage Stress Tests with 1/E model…...………….. 12
2.6.1 Stress Time and Stress Voltage……………………………..... 12
2.6.2 Stress Test Vector Generation……………………………….. 13
Chapter3 PHASE LOCK LOOP ARCHITECTURE 15
3.1 PLL Architecture…………………………………………….. 15
3.2 Phase Frequency Detector......................................………….. 17
3.3 Charge Pump………….……………………………………... 22
3.4 Loop Filter…………………………………………………... 25
3.5 Voltage-Controlled-Oscillator(VCO)………………………... 27
3.6 Divider………………………………………………………. 31
3.7 System Simulation………...…..…………………………….. 32
Chapter4 STRESS TEST OF CMOS PLLS FOR RELIABILITY EEHANCEMENT 44
4.1 Conventional Stress Test:0-1 Tests and Iddq Tests………….. 34
4.2 Stressable Analysis of Dvdloped Stress Tests…………….…. 34
4.3 VCO…………………………………………………………. 43
4.4 Stress Vector for Stress PLL………...………………………. 45
4.5 Improvement………………………………………………… 48
Chapter5 SUMMARY and Future Work 52
5.1 Summary………….…………………………………………. 52
5.2 Future Research Work……………………………………...... 53
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指導教授 魏慶隆(Chin-Long Wey) 審核日期 2006-7-24
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