 |
|
|
|
以作者查詢圖書館館藏 、以作者查詢臺灣博碩士 、以作者查詢全國書目 、勘誤回報 、線上人數：36 、訪客IP：18.221.165.246
姓名 吳俊賢(Chun-Hsien Wu) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 應用於內嵌式記憶體之高效率診斷性資料壓縮與可測性方案
(Efficient Diagnostic Data Compression and DFT Schemes for Embedded Memory Applications)相關論文 檔案 [Endnote RIS 格式]
[相關文章]
[文章引用]
[完整記錄]
[館藏目錄]
[檢視]
- 本電子論文使用權限為同意立即開放。
- 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
- 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中) 在電子技術快速發展的現今，內嵌式記憶體的應用以及相關之測試技術已成為最重要的議題之一。本論文針對內嵌式記憶體以及其應用性電路，提出兩個記憶體測試/診斷相關性之技術。在第一部分，一項針對內嵌式記憶體之診斷性資料進行高效率壓縮的方案將被提出。利用應用於記憶體之March測試演算法本身的特性,此項技術可以有效地濾除大量的冗餘錯誤徵狀；同時，原本被內建於內嵌記憶體中之自我修復電路亦可被重複利用，以降低面積成本。由實驗結果可知，此資料壓縮技術對混合的錯誤型態分佈可達到93%的高壓縮率，對純然的單元性錯誤亦可達到75%的壓縮效率。因此，所提出之技術對於各種錯誤型態分佈皆可臻至高效率的壓縮效果；在第二部分中，具有自我測試能力之維特比解碼器設計將被提出。維特比解碼器為無線通訊中應用極廣之模組；為了確保電路能達到預期的解碼能力，確認解碼電路於產品生產後的正確性對電路設計者為一重要的前提。在此可測性設計方案中，解碼器本身的電路特性被利用來有效地簡化測試過程。藉著維特比電路本身的回授路徑，測試樣型的推導與傳遞過程將在論文中被呈現。此可測性方案可將測試樣型經邏輯電路送至後方的內嵌式記憶體，因此大大地提高了模組的測試完整度。一方面，電路中的邏輯與記憶單元將可以同時被測試；另一方面，內嵌式自我測試電路亦可提高時序相關之錯誤涵蓋率，對產品的品質與可靠度將有顯著提升。此自我測試方案對維特比解碼器中的邏輯電路可達到93.6%的stuck-at fault涵蓋率，而額外所付出之面積成本約為8.2%。
摘要(英) With the rapid development of electronic technology, the applications of embedded memories and relative testing techniques have become one of the most important subjects. For general embedded memories and their applications, this thesis presents two associated techniques of memory test/diagnosis. In the first part, a high-efficiency diagnostic data compression scheme is proposed. To the characteristic of March test algorithms, the proposed compression scheme can eliminate large amount of redundant fault syndromes. At the same time, the built-in self repair circuitry will be reused to reduce the area cost of the BISD design. The experimental results show that the compression scheme can reach 93% diagnostic data reduction ratio for mixed fault distributions; and 75% data reduction ratio is made for merely single cell faults with the simulation setting. It reveals that the proposed diagnostic data compression scheme exhibits excellent compression ability for all kinds of fault distributions. In the second part, a BISTed Viterbi decoder design is presented. A Viterbi decoder is a widely-used module in the field of wireless communication. To ensure the decoding ability of the decoder, it is an issue for IC designers to ascertain the correctness of the chips. In the proposed DFT scheme, the characteristic of a Viterbi decoder is used to facilitate the test procedures. With the intrinsic feedback path, the process of pattern deriving and delivering for a typical Viterbi decoder can be performed. The DFT scheme makes the patterns go through the logic circuit, and then to the subsequent embedded memory, enhancing the test integrity of a Viterbi decoder. In the way, both the testing for logic and that for memory components can proceed simultaneously; on another hand, the embedded BIST module can cover more time-associated faults; it will advance the quality and reliability of the Viterbi decoder design. The proposed DFT scheme can reach 93.6% fault coverage for stuck-at faults of the logic circuit in a typical Viterbi decoder, and the area overhead is around 8.2%
關鍵字(中) ★ 自我診斷
★ 自我測試
★ 維特比
★ 內嵌式記憶體關鍵字(英) ★ BISD
★ BIST
★ viterbi
★ embedded memory論文目次 Chapter 1 Introduction …………………………………………………... 1
Chapter 2 Data Compression Techniques for Embedded Memories ….. 6
2.1. Preliminary ………………………………………………….... 6
2.2. The Compression Scheme of Diagnostic Data ………………. 9
2.2.1. Hamming Syndrome Elimination …………………………… 10
2.2.2. Fault Address Elimination …………………………………… 14
2.3. Architecture of the Built-In Self-Diagnosis Circuit ………… 28
2.4. Data Exportation Mechanism ……………………………….. 32
2.5. Codeword Format ……………………………………………. 36
2.6. Analysis for Area vs. Compression Efficiency ……………… 42
2.7. Experimental Results ………………………………………… 46
Chapter 3 Built-In Self-Test Scheme for Viterbi Decoder ……………… 52
3.1 Preliminary …………………………………………………… 52
3.1.1. Viterbi Algorithm and Trellis Diagram …………………….. 54
3.1.2. Viterbi Decoder ………………………………………………. 57
3.2. Testability Analysis for ACS Unit …………………………… 59
3.3. Proposed Test Strategy with PM Feedback ………………… 69
3.4. Experimental Results ………………………………………… 77
Chapter 4 Conclusions and Future Works ……………………………… 83
Reference …………………………………………………………………….. 85
參考文獻 [1] Po-Kai Chen, Yu-Tsao Hsing, and Cheng-Wen Wu, ”On Feasibility of HOY-A Wireless Test Methodology for VLSI Chips and Wafers”, International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2006, pp.1-4
[2] Cheng-Wen Wu, Chih-Tsun Huang, Shi-Yu Huang, Po-Chiun Huang, Tsin-Yuan Chang, and Yu-Tsao Hsing, “The HOY Tester - Can IC Testing Go Wireless?”, International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2006, pp.1-4
[3] Te-Wen Ko, Yu-Tsao Hsing, Cheng-Wen Wu, and Chih-Tsun Huang, “Stable Performance MAC Protocol for HOY Wireless Tester under Large Population”, International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-27 April 2007, pp.1-4
[4] D. A. Huffman, “A Method for the Construction of Minimum-Redundancy Codes,” in Proc. IRE 1952, vol. 40, pp. 1098–1101.
[5] S. W. Golomb, “Run-Length Encodings,” IEEE Trans. Inform. Theory, vol. 12, no. 3, pp. 399–401, Jul. 1966.
[6] Chandra A. and Chakrabarty K., "Test Data Compression and Test Resource Partitioning for System-on-a-Chip using Frequency-Directed Run-Length (FDR) codes", IEEE Trans. on Computers, vol. 52, Issue 8, pp. 1076-1088, Aug. 2003
[7] Jin-Fu Li and Cheng-Wen Wu, "Memory Fault Diagnosis by Syndrome Compression", in Proc. Design, Automation and Test in Europe (DATE), 13-16 Mar. 2001, pp. 97-101
[8] Jin-Fu Li, Ruey-Shing Tzeng and Cheng-Wen Wu, "Using Syndrome Compression for Memory Built-In Self-Diagnosis", in Proc. International Symposium on VLSI technology, Systems, and Applications, 18-20 Apr. 2001, pp 303 - 306
[9] Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Shen-Tien Lin and Wen-Ching Wu, "Embedded Memory Diagnostic Data Compression Using Differential Address", IEEE International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), 27-29 Apr. 2005, pp. 20-23
[10] Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Yeong-Jar Chang and Wen-Ching Wu, "A Memory Built-In Self-Diagnosis Design with Syndrome Compression", in Proc. IEEE International Workshop on Current and Defect Based Testing (DBT), 25 Apr. 2004, pp. 99-104
[11] Chen, J.T., Khare, J., Walker, K., Shaikh, S., Rajski, J. and Maly W., "Test Response Compression and Bitmap Encoding for Embedded Memories in Manufacturing Process Monitoring", in Proc. International Test Conference, 30 Oct.-1 Nov. 2001, pp. 258-267
[12] C.-F Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W.Wu, “Error Catch and Analysis for Semiconductor Memories Using March Tests”, in Proc. IEEE Int. Conf. Computer-Aided Design (ICCAD), San Jose, Nov. 2000, pp. 468-471
[13] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-In Redundancy Analysis for Memory Yield Improvement”, IEEE Trans. Reliab., vol. 52, no. 4, pp. 386-399, Dec. 2003.
[14] T.-W. Tseng, J.-F. Li, and C.-C. Hsu, “ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs”, IEEE Trans. on VLSI Systems, vol. 18, issue 6, pp. 921-932, Jun. 2010
[15] A. J. Viterbi, “Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm,” IEEE Trans. Inform. Theory, vol. IT-13, pp. 260–269, Apr. 1967
[16] G. D. Forney, Jr., “The Viterbi Algorithm,” Proc. IEEE, vol. 61, pp. 268–278, Mar. 1973
[17] P. J. Black and T. H. Meng, “A 140-Mb/s 32-State Radix-4 Viterbi Decoder,” IEEE J. Solid-State Circuits, vol. 27, pp. 1877–1885, Dec. 1992
[18] C. B. Shung, H-D. Lin, R. Cypher, P. H. Siege1 and H. K. Thapar, “Area-Efficient Architecture for the Viterbi Algorithm Part 11: Applications,” IEEE Trans. on Commun., vol. 41, pp. 802-807, May 1993
[19] M. Boo, F. Arguello, J. D. Bruguera, R. Doallo and E. L. Zapata, “High-Performance LSI Architecture for the Viterbi Algorithm,” IEEE Trans. on Commun., vol. 45, pp. 168-176, Feb. 1997
[20] Gennady Feygin and P.G. Gulak. .Architectural Tradeoff for Survivor Sequence Memory in Viterbi Decoder.. IEEE Trans. on Commun., vol.. 41, pp. 425-429, 1998
[21] Kajihara S. and Sasao T., “On the Adders with Minimum Tests,” in Proc. Sixth Asian Test Symposium (ATS), 17-18 Nov. 1997, pp. 10 - 15
指導教授 李進福(Jin-Fu Li) 審核日期 2010-8-10 推文 plurk
funp
live
udn
HD
myshare
netvibes
friend
youpush
delicious
baidu
網路書籤 Google bookmarks
del.icio.us
hemidemi
facebook
twitter
google
reddit