鍺浮點記憶體之研製

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姓名

吳榮軒(Jung-Hsiuan Wu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

鍺浮點記憶體之研製
(Ge floating dot memory)

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摘要(中)

在本論文中，利用低壓化學氣相沈積系統沈積複晶矽鍺團並藉由氧化之方式形成鍺奈米晶粒製作出鍺浮點記憶體。在製作過程中，我們利用橢圓儀開發了非破壞性的表面狀態檢測方法，以判別晶粒形成與否。此外，鍺浮點記憶體在閘極蝕刻這部分也是製程中之重要關鍵，因為鍺浮點記憶體閘堆疊層中之鍺奈米晶粒是否蝕刻乾淨會嚴重影響後續之製程與元件特性。
在製作鍺浮點記憶體之同時，我們也製作了矽鍺浮閘記憶體、矽鍺浮閘電容和鍺浮點電容。我們利用製作出來之元件做了以下幾項電性量測包含：電容量測、儲存時間量測、脈波量測、耐用性量測等。藉由以上之量測，我們可以清楚知道我們製作元件之特性，並得知影響元件特性之原因與元件結構之關鍵點。

摘要(英)

Abstract
In this thesis, we utilize the method of thermal oxidation poly SiGe to form Ge nanocrystals and then fabricate the Ge nanocrystals transistor. In the process of fabrication, we have also developed the undestructive method to check surface state of the sample by Ellipsometer. Besides, the gate etching in formation of Ge nanocrystals transistor is very important. Because removing Ge nanocrystals embedded in gate stacked greatly effects the following fabrication and characteristics of device.
We have fabricated Ge nanocrystals MOS capacitors and FET by using the method of thermal oxidation poly SiGe to form Ge nanocrystals. After formation, we take some measurements included capacitance measurement, Retention time measurement, pulse width measurement and endurance measurement. According to the result of measurements we can easily realize the characteristics of our device and the problems of device structure.

關鍵字(中)

★ 非揮發性記憶體
★ 鍺浮點記憶體

關鍵字(英)

★ Ge floating dot memory
★ nonvolatile memory

論文目次

目錄
第一章介紹 ...............................................................1
1-1 前言.................................................................1
1-2 研究動機.............................................................1
1-3 研究目的與應用.......................................................3
第二章快閃記憶體之操作原理........................................7
2-1 前言.................................................................7
2-2 快閃記憶體之寫入與抹除原理...........................................7
2-3 穿隧機制.............................................................8
2-3-1 F-N 穿隧效應.....................................................8
2-3-2 通道熱電子注入...................................................9
2-3-3 直接穿隧效應.....................................................9
2-4 結論................................................................10
第三章鍺浮點記憶體之製程與開發.......................................14
3-1 前言.... ...........................................................14
3-2 閘堆疊層製作........................................................14
3-2-1 沈積系統........................................................14
3-2-2 閘堆疊層沈積流程................................................15
3-2-3 複晶矽鍺薄膜之潛伏期............................................15
3-2-4 複晶矽鍺層沈積實驗..............................................16
3-2-5 非破壞性表面狀態之檢測..........................................17
3-2-5.1 橢圓儀系統與操作原理........................................17
3-2-5.2 橢圓儀模擬..................................................18
3-2-6 氧化複晶矽鍺團形成鍺奈米晶粒....................................20
3-3 閘極製作............................................................22
3-3-1 閘極蝕刻之時間..................................................22
3-3-2 接觸窗口之問題..................................................22
第四章元件量測與分析...................................................35
4-1 前言................................................................35
4-2 矽鍺浮閘記憶體之失敗性分析..........................................35
4-2-1 矽鍺浮閘電容之電流密度對電場(J-E)量測...........................35
4-2-2 矽鍺浮閘電容之電容對電壓(C-V)量測...............................36
4-2-3 PN 接面之量測與分析.............................................39
4-2-4 矽鍺浮閘記憶體之失敗性分析......................................40
4-3 鍺浮點電容之量測....................................................41
4-3-1 鍺浮點電容之C-V 分析...........................................41
4-3-2 儲存時間測試...................................................42
4-4 浮點電晶體量測.....................................................43
4-4-1 儲存時間測試....................................................43
4-4-2 脈波量測........................................................43
4-4-3 耐用性量測......................................................44
4-5結論................................................................45
第五章總結與未來展望..................................................58
參考文獻..................................................................59

參考文獻

參考文獻資料
[1] Sandip Tiwari, Farhan Rana, Hussein Hanafi, Allan Hartstein, Emmanuel F. Crabbe´, Kevin Chan, “A silicon nanocrystals based memory,” Appl. Phys. Lett. 68, pp1377, 1996.
[2] Donald A. Neamen, “Semiconductor physics and device,” p.43
[3] Stanley. Wolf., “Silicon Processing For The VLSI Era Volume 3:The Submicron MOSFET, ” Lattice Press, p.436, 1995.
[4] 莊達人, “VLSI 製造技術, ” pp.233-234
[5] Tsu-Jae King, Krishna C. Saraswat, “Deposition and Properties of Low-Pressure Chemical Vapor Deposited Polycrystalline Silicon Germanium Film, ” J. Electrochem. Soc., vol.141, No.8, pp.2235, 1994.
[6] Min Cao, Albert Wang, Krishna C. Saraswat, “Low Pressure Chemical Vapor Deposition of Si1-xGex Film on SiO2,” J. Electrochem. Soc., vol.141, No.8, pp.1566, 1995.
[7] M. Yoshimaru, J. Miyano, N. Inoue, A. Sakamoto, S. You, H. Tamura, M. Ino, “RUGGED SURFACE POLY-Si ELECTRODE AND LOW TEMPERATURE
DEPOSITED Si3N4 FOR 64 MBIT AND BEYOND STC DRAM CELL, ” IEDM, 59
pp.661, 1990.
[8] Hirohito Watanabe, Akira Sakai, Toru Tatsumi, Taeko Niino, “Hemispherical Grain Silicon for High Density DRAMs, ” SOLID STATE TECHNOLOGY, pp.30, July, 1992.
[9] T. Baron, B. Pelissier, L. Perniola, F. Mazen, J. M. Hartmann, G. Rolland, “Chemical vapor deposition of Ge nanocrystals on SiO2, ” American Institute of Physis, Vol. 83, No. 7, pp.1444-1446, 2003.
[10] M. Kanoun, A. Souifi, T. Baron, F. Mazen, ”Electrical study of Ge nanocrystal based metal-oxide-semiconductor structure for p-type nonvolatile memory applications, ” American Institute of Physis, Vol. 84, No. 25, pp. 5079-5081, 2004.
[11] Jing Hao Chen, Ying Qian Wang, Won Jong Yoo, ”Nonvolatile Flash Memory Device Using Ge Nanocrystal Embedded in HfAlO High K Tunneling and Control Oxides: Device Fabrication and Electrical Performance, ” IEEE TRANSACTIONS ON ELECTRON DEVICE, Vol. 51, No. 11, pp. 1840, 2004.

指導教授

李佩雯(Pei-Wen Li)

審核日期

2006-7-12

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