參考文獻 |
Chapter 1
[1]S. Maeda, Y. Yamaguchi, I. J. Kim, T. Iwamatsu, T. Ipposhi, S. Miyamoto, S. Maegawa, K. Ueda, K. Mashiko, Y. Inoue, T. Nishimura, and H. Miyoshi, “Analysis of delay time instability according to the operating frequency in field shield isolated SOI circuits,” IEEE Trans. Electron Devices, vol. 45, pp.1479-1486, 1998.
[2]S. Maeda, Y. Hirano, Y. Yamaguchi, T. Iwamatsu, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, H. Abe, and T. Nishimura, “Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, pp.151-158, 1999.
[3]T. Iwamatsu, Y. Yamaguchi, Y. Inoue, T. Nishimura, and N. Tsubouchi, “CAD-compatible high-speed CMOS/SIMOX gate array using field- shield isolation,” IEEE Trans. Electron Devices, vol. 42, pp.1934-1939, 1995.
[4]T. Iwamatsu, Y. Yamaguchi, K. Ueda, K. Mashiko, Y. Inoue, and T. Hirao, “High-speed 0.5 mm SOI 1/8 frequency divider with body-fixed structure for wide range of applications,” in Ext. Abst. SSDM, PP.575, 1995.
[5]W. Chen, Y. Taur, D. Sadana, K. A. Jenkins, J. Sun, and S. Cohen, “Suppression of the SOI floating-body effects by linked-body device structure,” in Symp. VLSI Tech., pp. 92, 1996.
[6]J. B. Kuo, and Ker-Wei Su, 1998, CMOS VLSI ENGINEERING Silicon-on Insulator (SOI), Kluwer Academic Publishers.
[7]K. Kato, T. Wada, and K. Taniguchi, “Analysis of kink characteristics in silicon-on-insulator MOSFET’s using two-carrier modeling,” IEEE Trans. Electron Devices, vol. 32, pp.458-462, 1985.
[8]S. P. Edwards, K. J. Yallup, and K. M. D. Meyer, “Two-dimensional numerical analysis of the floating region in SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 35, pp.1012-1020, 1988.
[9]K. K. Young and J. A. Burns, “Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFET’s,” IEEE Trans. Electron Devices, vol. 35, pp.426-431, 1988.
[10]M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi, and K. Natori, “Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, pp.2015-2021, 1990.
[11]J. R. Davis, A. E. Glaccum, K. Reeson, and P. L. F Hemment, “Improved subthreshold characteristics of n-channel SOI transistors,” IEEE Electron Device Letters, vol. 7, pp.570-572, 1986.
[12]J. G. Fossum, R. Sundaresan, and M. Matloubian, “Anomalous subtreshold current-voltage characteristics of n-channel SOI MOSFET’s,” IEEE Electron Device Letters, vol. 8, pp.544-546, 1987.
[13]M. Terauchi, M. Yoshimi, A. Murakoshi, and Y. Ushiku, “Supression of the floating-body effects in SOI MOSFETs by bandgap engineering,” in VLSI Sym. Dig. Tech. Papers, pp.35-36, 1995.
[14]J. P. Colinge, “Silicon-on-insulator technology: materials to VLSI,” Chapter 5, Kluwer Academic Publishers, 2004.
[15]C. C. Chang, “Improvement of 2-D and 3-D Semiconductor Device Simulation Using Equivalent-circuit Model,” Ph.D. dissertation, National Central University, Taiwan, 2006.
[16]H. K. Lim, and J. G. Fossum, “Threshold Voltage of Thin-Film Silicon-On-Insulator (SOI) MOSFET’s,” IEEE Trans. Electron Devices, Vol. 30, No. 10, pp. 1244-1251, Oct. 1983.
[17]K. K. Young, “Analysis of Conduction in Fully Depleted SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. 36, No. 3, pp. 504-506, March 1989.
[18]E. R. Worley, “Theory of the Fully Depleted SOS/MOS Transistor,” Solid State Electronics, Vol. 23, pp. 1107-1111, 1980.
[19]J. B. McKitterick, and A. L. Caviglia, “An Analytical Model for Thin SOI Transistors,” IEEE Trans. Electron Devices, Vol. 36, No. 6, pp. 1133-1138, June 1989.
[20]F. Balestra, M. Benachir, J. Brini, and G. Ghibaudo, “Analytical Models of Subthreshold Swing and Threshold Voltage for Thin- and Ultra-Thin-Film SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. 37, No. 11, pp. 2303-2311, Nov. 1990.
[21]Y. Inoue, Y. Yamaguchi, T. Yamaguchi, J. Takahashi, T. Iwamatsu, T. Wada, Y. Nishimura, T. Nishimura, and N. Tsubouchi, “Selection of Operation Mode on SOI/MOSFET’s for High-Resistivity Load Static Memory Cell,” SOI Conf. Dig., pp. 94-95, 1993.
[22]M. Haond, and M. Tack, “Rapid Electrical Measurements of Back Oxide and Silicon Film Thickness in an SOI CMOS Process,” IEEE Trans. Electron Devices, Vol. 38, No. 3, pp. 674-676, March 1991.
[23]J. B. Kuo, and Ker-Wei Su, 1998, CMOS VLSI ENGINEERING Silicon-on Insulator (SOI), Kluwer Academic Publishers, Chapter 4.
[24]H. K. Gummel, “A Self-consistent Iterative Scheme for One-dimensional Steady State Transistor Calculations,” IEEE Trans. Electron Devices, pp.455-465, 1964.
[25]ISE TCAD Manuals, release 8.5.
Chapter 2
[26]B. J. Baliga, “High Voltage Integrated Circuits,” IEEE Press, 1988.
[27]C. M. Liu, K. H. Lou, and J. B. Kuo, “77 K versus 300 K Operation: The Quasi-Saturation Behavior of a DMOS Device and its Fully Analytical Model,” IEEE Trans. Electron Devices, Vol. 40, No. 9, pp. 1636-1644, September 1993.
[28]E. Arnold, T. Letavic, and H. Bhimnathwala, “High-Temperature Off-State Characteristics of Thin-SOI Power Devices,” IEEE Electron Device Letters, Vol. 17, No. 12, pp. 557-559, December 1996.
[29]陳蓮春(2000),電功率MOSFET應用技術,建興出版社。
[30]胡永昌(2001),分離式元件市場與發展趨勢。元件科技雜誌,25期,94頁。
[31]U.S. Patent Nos. 4,975,751.
[32]U.S. Patent Nos. 5,091,336.
[33]B. J. Baliga, “Evolution of MOS-Bipolar Power Semiconductor Technology,” proceeding of the IEEE, Vol. 76, No. 4, 1988.
[34]M. J. Declerg, and J. D. Plummer, “Avalanche breakdown in high voltage DMOS devices,” IEEE Trans. Electron Devices, Vol. ED-23, pp.1-6, 1976.
[35]B. J. Baliga, M. S. Adler, P. V. Gray, and R. P. Love, “The Insulated Gate Rectifier (IGR): A New Power Switching Device,” IEDM Technical Digest, pp.264-265, Dec. 1982.
[36]J. P. Russel, A. M. Goodman, L. A. Goodman, and J. M. Neilson, “The COMFET-A New High Conductance MOS-Gated Devices,” IEEE Electron Device Letters, Vol. ED-4, No. 3, pp.63-65, March 1983.
[37]B. J. Baliga, M. S. Adler, P. V. Gray, R. P. Love, and N. D. Zomer, “The Insulated Gate Transistor: A New Three-Terminal MOS-Controlled Bipolar Power Device,” IEEE Trans. Electron Devices, Vol. ED-31, No. 6, pp.821-828, June 1984.
[38]B. J. Baliga, “Trends in Power Semiconductor Devices,” IEEE Trans. Electron Devices, Vol. 43, pp.1717-1731, 1996.
Chapter 3
[39]C. M. Snowden, 1986, Introduction to Semiconductor Device Modelling, World Scientific, Chapter 4.
[40]Y. T. Tsai, , and T. C. Ke, “Electrode Separation Method to the Boundary Condition for a-Si TFT Mixed-level Simulation,” International Journal of Numerical Modelling: Electronic Networks, Devices, and Fields, Vol. 11, No. 2, pp. 123-130, 1998.
[41]Y. T. Tsai, C. Y. Lee, and M. K. Tsai, “Levelized Incomplete LU Method and Its Application to Semiconductor Device Simulation,” Solid-State Electronics, Vol. 44, No. 6, pp. 1069-1075, 2000.
[42]Y. T. Tsai, C. F. Dai, and M. K. Tsai, “An Improved Levelized Incomplete LU Method And Its Application to 2D Semiconductor Device Simulation,” Journal of Chinese Institute of Engineers, Vol. 24, No. 3, pp. 389-396, 2001.
[43]K. Kato, T. Wada, and K. Taniguchi, “Analysis of Kink Characteristics in Silicon-on-insulator MOSFETs Using Two-carrier Modeling,” IEEE Trans. Electron Devices, Vol. 32, No. 2, pp. 458-462, 1985.
[44]S. P. Edwards, K. J. Yallup, and K. M. D. Meyer, “Two-dimensional Numerical Analysis of the Floating Region in SOI MOSFETs,” IEEE Trans. Electron Devices, Vol. 35, No. 7, pp. 1012-1020, 1988.
[45]K. K. Young, and J. A. Burns, “Avalanche-induced Drain-source Breakdown in Silicon-on-insulator n-MOSFETs,” IEEE Trans. Electron Devices, Vol. 35, No. 4, pp. 426-431, 1988.
[46]M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi, and K. Natori, “Analysis of the Drain Breakdown Mechanism in Ultra-thin-film SOI MOSFETs,” IEEE Trans. Electron Devices, Vol. 37, No. 9, pp. 2015-3021, 1990.
[47]J. R. Davis, A. E. Glaccum, K. Reeson, and P. L. F. Hemment, “Improved Subthreshold Characteristics of N-channel SOI Transistors,” IEEE Electron Device Letters, Vol. 7, No. 10, pp. 570-572, 1986.
[48]J. G.. Fossum, R. Sundaresan, and M. Matloubian, “Anomalous Subtreshold Current-voltage Characteristics of N-channel SOI MOSFETs,” IEEE Electron Device Letters, Vol. 8, No. 11, pp. 544-546, 1987.
[49]C. H. Ho, C. C. Chang, S. J. Li, and Y. T. Tsai, “The Branch-Cut Method and Its Applications in Two-Dimensional Device Simulation,” ACTA International Journal of Modelling and Simulation, Vol. 29, No. 1, pp. 1-6, 2009.
[50]J. P. Colinge, 2004, Silicon-on-insulator Technology: Materials to VLSI, Kluwer Academic Publishers, Chapter 5.
[51]J. Tihani, and H. Schlotterer, “Properties of ESFI MOS Transistors Due to the Floating Substrate and the Finite Volume,” IEEE Trans. Electron Devices, Vol. 22, No. 11, pp. 1017-1023, 1975.
[52]J. Colinge, “Reduction of Kink Effect in Thin-film SOI MOSFETs,” IEEE Electron Device Letters, Vol. 9, No. 2, pp. 97-99, 1988.
[53]J. B. Kuo, and S. C. Lin, 2001, Low-voltage SOI CMOS VLSI Devices and Circuits, John Wiley & Sons, Inc., Chapter 2.
[54]G. G. Shahidi, “SOI Technology for the GHz Era,” IBM Journal of Research and Development, Vol. 46, No. 2, pp. 121-131, 2002.
Chapter 4
[55]S. Merchant, E. Arnold, H. Baumagart, S. Mukherjee, H. Pein, and R. Pinker, “Realization of High Breakdown Voltage (>700 V) in Thin SOI Devices,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 31-35, 1991.
[56]S. K. Chung, S. Y. Han, J. C. Shin, Y. I. Choi, and S. B. Kim, “An Analytical Model for Minimum Drift Region Length of SOI RESURF Diodes,” IEEE Electron Device Letters, Vol. 17, pp. 22-24, 1996.
[57]Z. Sun, W. Sun, and L. Shi, “Modeling Kirk Effect of RESURF LDMOS,” Solid-State Electronics, Vol. 49, pp.1896-189, 2005.
[58]Y. S. Huang, and B. J. Baliga, “Extension of RESURF Principle to Dielectrically Isolated Power Devices,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 27-30, 1991.
[59]S. Merchant, E. Arnold, H. Baumagart, R. Egloff, T. Letavic, S. Mukherjee, and H. Pein, “Dependence of Breakdown Voltage on Drift Length and Buried Oxide Thickness in SOI RESURF LDMOS Transistors,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 124-128, 1993.
[60]D. Jaume, G. Charitat, J.M. Reynes, and P. Russel, “High-voltage Planar Devices Using Field Plate and Semi-resistive Layers,” IEEE Trans. Electron Devices, Vol. 38, pp. 1681-1684, 1991.
[61]T. Matsushita, T. Aoki, T. Otsu, H. Yamoto, H. Hayashi, M. Okayama, and Y. Kawana, “Semi-insulating Polycrystalline-Silicon (SIPOS) Passivation Technology,” Jpn. J. Appl. Phys., Vol. 15, pp. 35-40, 1976.
[62]A. Nakagawa, Y. Yamaguchi, N. Yasuhara, K. Hirayama, and H. Funaki, “New High Voltage SOI Device Structure Eliminating Substrate Bias Effects,” IEDM Tech. Dig., pp. 477-480, 1996.
[63]ISE TCAD Manuals, release 9.5.
[64]T. Stockmeier, and K. Lilja, “SIPOS-passivation for High Voltage Power Devices with Planar Junction Termination,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 145-148, 1991.
[65]S. Mukherjee, C. J. Chou, K. Shaw, D. McArthur, and V. Rumennik, “The Effect of SIPOS Passivation on DC and Switching Performance of High Voltage MOS Transistors,” IEDM Tech. Dig., pp. 646-649, 1986.
[66]T. Sakai, K. C. So, Z. Shen, and T. P. Chow, “Modeling and Characterization of SIPOS Passivated, High Voltage, N- and P-channel Lateral RESURF type DMOSFETs,” IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 288-292, 1992.
[67]S. K. Chung, and S. Y. Han, “Analytical Model for the Surface Field Distribution of SOI RESURF Device,” IEEE Trans. Electron Devices, Vol. 45, pp. 1374-1376, 1998.
[68]R. A. Kokosa, R. L. Davies, “Avalanche Breakdown of Diffused Silicon P-N Junction,” IEEE Trans. Electron Devices, Vol. 13, pp. 874-881, 1966.
[69]R. V. Overstraeten, H. D. Man, “Measurement of the Ionization Rates in Diffused Silicon P-N Junctions,” Solid-State Electronics, Vol. 13, pp. 583-608, 1970.
[70]W. Fulop, “Calculation of Avalanche Breakdown Voltages of Silicon P-N Junction,” Solid-State Electronics, Vol. 10, pp. 39-43, 1967.
[71]S. K. Chung, D. K. Shin, “An Analytical Model for Interaction of SIPOS Layer with Underlying Silicon of SOI RESURF Devices,” IEEE Trans. Electron Devices, Vol. 46, pp. 1804-1807, 1999.
Chapter 5
[72]S. Merchant, E. Arnold, H. Baumagart, S. Mukherjee, H. Pein, and R. Pinker, “Realization of High Breakdown Voltage (>700 V) in Thin SOI Devices,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 31-35, 1991.
[73]S. K. Chung, S. Y. Han, J. C. Shin, Y. I. Choi, and S. B. Kim, “An Analytical Model for Minimum Drift Region Length of SOI RESURF Diodes,” IEEE Electron Device Letters, Vol. 17, pp. 22-24, 1996.
[74]Z. Sun, W. Sun, and L. Shi, “Modeling Kirk Effect of RESURF LDMOS,” Solid-State Electronics, Vol. 49, pp.1896-189, 2005.
[75]Y. S. Huang, and B. J. Baliga, “Extension of RESURF Principle to Dielectrically Isolated Power Devices,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 27-30, 1991.
[76]S. Merchant, E. Arnold, H. Baumagart, R. Egloff, T. Letavic, S. Mukherjee, and H. Pein, “Dependence of Breakdown Voltage on Drift Length and Buried Oxide Thickness in SOI RESURF LDMOS Transistors,” Proc. IEEE Int. Symp. Power Semiconductor Devices and IC’s, pp. 124-128, 1993.
[77]C. H. Ho, C. N. Liao, F. T. Chien, and Y. T. Tsai, “An Analytical Model for Silicon-on-Insulator Reduced Surface Field Devices with Semi-Insulating Polycrystalline Silicon Shielding Layer,” Japanese Journal of Applied Physics, Vol. 47, No. 7, pp. 5369-5373, 2008.
[78]A. Nakagawa, Y. Yamaguchi, N. Yasuhara, K. Hirayama, and H. Funaki, “New High Voltage SOI Device Structure Eliminating Substrate Bias Effects,” IEDM Tech. Dig., pp. 477-480, 1996.
[79]D. W. Tong, J. L. Benjamin, and W. R. V. Dell, “Interface Effects of SIPOS Passivation,” IEEE Trans. Electron Devices, Vol. 33, pp. 779-787, 1986.
[80]S. M. Sze, 1981, Physics of Semiconductor Devices 2nd edn, New York: Wiley.
Chapter 6
[81]C. H. Ho, and Y. M. Hsin, “The Process Integration of GaN BJT and MOSFET,” Electron Devices and Materials Symposium, 2005, Kaohsiung, Taiwan.
[82]W. C. Lai, M. Yokoyama, C. C. Tsai, C. S. Chang et al., “Electrical Properties of Multiple High-Dose Si Implantation in p-GaN,” Japanese Journal of Applied Physics, Vol. 38, pp. L802-L804, 1999.
[83]Y. Irokawa, Y. Nakano, M. Ishiko, T. Kachi et al., “MgO/p-GaN Enhancement Mode Metal-oxide Semiconductor Field-effect Transistor,” Applied Physics Letters, Vol. 84, No. 15, pp. 2919-2921, 2004.
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