全數位式高解析度快速鎖定時脈同步電路之設計與實現

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洪凱尉(Kai-Wei Hong) 查詢紙本館藏

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電機工程學系

論文名稱

全數位式高解析度快速鎖定時脈同步電路之設計與實現
(Design and Implementation of All-Digital High Precision Fast Locking Clock Synchronization Circuits)

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摘要(中)

隨著系統晶片(System-on-chip, SoC)的蓬勃發展，其時脈訊號的同步也將成為一個重要的問題。由於人類通訊需求的進步，SoC也大量的被應用於行動手持通訊系統中。為了增加使用時間以及增加電池壽命，因此在手持系統中，降低功率消耗將會是一個被重視的問題。在系統應用中，為了將低功率消耗，會使用頻率調整技術或將部分應用規格晶片(Application-Specific Integrated Chips, ASICs)或矽晶片(Silicon Intellectual Properties (IPs)進入休眠模式。因此能快速鎖定的全數位式時脈同步電路很適合應用於低功率消耗的系統中。
傳統的同步鏡射電路 (Conventional Synchronous Mirror Delay, CSMD)是一種全數位式時脈同步電路，其可在兩個週期內完成時脈的同步，且架構簡單。很適合應用於低功率消耗的系統中且不用佔用太大的面積。然而，CSMD沒辦法接收超過50%責任週期的時脈訊號、鎖定後的靜態相位誤差也較差、操作範圍狹窄以及容易被負載效應所影響。上述的缺點，限制了CSMD在系統中的應用。
本文提出了四個以CSMD為基本的全數位式時脈同步電路，其保留了CSMD的優點同時改善了CSMD的缺點。第一，我們需要解決輸入脈波寬度的問題。我們改良了傳統的鏡射控制電路，我們使用D型正反器(D-type Flip-Flop, DFF)取代了AND邏輯閘，由於DFF為一邊緣觸發電路，因此改良式的鏡射控制電路可有效的改善輸入脈波寬度的問題。第二，在電路初步鎖定後，我們加入了旋轉式控制的微調機制，來偵測輸入以及輸出訊號的相位差，在進行細部的相位調整，達成改善相位誤差的目的，同時應用在動態頻率調整系統。第三，我們使用了一個新型的架構來解決負載效應的影響。此架構可偵測輸出驅動器受到負載的影響後，進而控制延遲線來校正輸出負載的影響。最後，為了增加輸出範圍且又不需增加太多的面積，我們使用了頻率選擇器來增加電路操作範圍。因此我們所提出的時脈同步電路很適合應用於SoC或低功率消耗需求的系統中。

摘要(英)

Nowadays, the complexity and operating frequency of System-on-a-Chips (SoCs) are growing with the evolution of the CMOS technology. The clock synchronization will become a serious problem in an SoC. The SoCs are widely applied in portable electronic device. The portable electronic devices require chips with low power consumption in order to make the battery life longer. Some application-specific integrated chips (ASICs) or silicon intellectual properties (IPs) might enter a hibernation mode or use a dynamic frequency to conserve energy. The all-digital clock synchronization circuits achieves fast locking, therefore, they are suitable to apply in SoCs.
The conventional synchronous mirror delay (CSMD) circuit is a kind of digital clock synchronization circuits. The CSMD circuit with a simple structure synchronizes the clock in two clock cycles. The CSMD circuit is suitable as a digital clock synchronization circuit in SoCs. The CSMD, however, cannot accept the clock signal with more than 50% duty cycle, has poor static phase error, has narrow operating range, and is affected by the output loading effect. These problems limit the application of the CSMD.
This thesis proposes four clock synchronization circuits based on CSMD. The proposed circuits keep the advantages of CSMD and overcome the disadvantages of CSMD. First, a modified the mirror control circuit (MMCC) utilizes the D-type flip-flops instead of AND gates to solve the input duty cycle problem. The MMCC overcomes the input duty cycle problem because the DFF is an edge-trigger device. Second, a cyclic-based fine tune circuit detects the phase error between input and output signals after coarse locking. The fine tune circuit enhances the static phase error and achieves dynamic phase error compensation. Third, a new topology is used against the output loading effect. The new topology detects and calibrates the variations caused by output loading effect. Finally, a frequency selector is used to extend the operating range. The frequency selector not only has a small area but also extends the operating range. The proposed synchronization circuits suitable apply in the SoCs or the low power requirement systems to eliminate the clock skew.

關鍵字(中)

★ 全數位式時脈同步電路
★ 全數位式延遲鎖定迴路
★ 高解析度
★ 快速鎖定

關鍵字(英)

★ High Precision
★ All-Digital Delay-Locked Loop
★ Fast Locking
★ ADDLL
★ All-Digital Clock Synchronization Circuit

論文目次

摘要......................................................i
Abstract................................................iii
誌謝......................................................v
Contents................................................vii
Figure Captions................................................xii
Table Captions...............................................xvii
Chapter 1 Introduction.....................................1
1.1 Demand of Clock Synchronization..................1
1.2 Motivation.......................................3
1.3 Thesis Organization..............................5
Chapter 2 Fundamentals of Clock Synchronization Circuits...7
2.1 Clock Synchronization Circuits...................7
2.1.1 Analog Clock Synchronization Circuits............7
2.1.2 All-Digital Clock Synchronization Circuits.......8
2.2 Analog Clock Synchronization Circuits............8
2.2.1 Phase-Locked Loop................................8
2.2.2 Delay-Locked Loop...............................11
2.3 All-Digital Clock Synchronization Circuits......13
2.3.1 All-Digital Phase-Locked Loop...................13
2.3.2 All-Digital Delay-Locked Loop...................16
2.4 Synchronous Mirror Delay (SMD) Circuit..........17
2.4.1 Conventional SMD Circuit........................17
2.4.2 Interleaved SMD Circuit.........................20
2.4.3 Direct De-skew SMD Circuit......................21
2.4.4 Successive Approximation Register SMD Circuit...22
2.4.5 Arbitrary Duty Cycle SMD circuit................23
2.5 Summary.........................................24
Chapter 3 A Dynamic Tracking and Phase Error Compensation Clock De-skew Buffer.....................................26
3.1 Dynamic Tracking Clock De-skew Buffer...........26
3.1.1 Proposed DTCSB Architecture.....................26
3.1.2 Operation and Timing Analysis...................27
3.2 Implementation of DTCSB.........................30
3.2.1 Coarse Tune Structure...........................30
3.2.2 Modified Mirror Control Delay...................31
3.2.3 Dynamic Phase Error Compensation................31
3.2.4 Fine Tune Structure.............................32
3.3 Simulation Results..............................35
3.3.1 System Simulation Results.......................35
3.4 Measurement Environment Setup and Experiment Results..................................................37
3.4.1 Concept.........................................37
3.4.2 Measurement Environment Setup...................37
3.4.3 Experiment Results..............................38
Chapter 4 A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit......................43
4.1 High Precision Fast Locking Clock Synchronization Circuit..................................................43
4.1.1 Proposed HPCS Architecture......................43
4.1.2 Operation and Timing Analysis...................45
4.2 Implementation of HPCS..........................49
4.2.1 Coarse and fine delay paths.....................49
4.2.2 Coarse tune Control Circuit.....................50
4.2.3 Fine tune Control Circuit.......................50
4.3 Simulation Results..............................53
4.3.1 System Simulation Results.......................53
4.3.2 Monte Carlo Analysis............................55
4.4 Measurement Environment Setup and Experiment Results..................................................58
4.4.1 Concept.........................................58
4.4.2 Measurement Environment Setup...................58
4.4.3 Experiment Results..............................58
Chapter 5 An All-Digital Clock Synchronization Buffer with One Cycle Dynamic Synchronizing..........................64
5.1 One Cycle Dynamic Synchronizing Clock Synchronization Buffer...................................64
5.1.1 Proposed DSCSB Architecture.....................65
5.1.2 Timing and Operation Analysis...................66
5.2 Implementation of DSCSB.........................70
5.2.1 Coarse Delay path...............................70
5.2.2 Coarse Tune Control Circuit.....................70
5.2.3 Fine Tune Structure.............................71
5.2.4 Dynamic Phase Error Compensation................71
5.3 Simulation Results..............................72
5.3.1 System Simulation Results.......................73
5.3.2 Monte Carlo Analysis............................74
5.4 Measurement Environment Setup and Experiment Results..................................................78
5.4.1 Concept.........................................78
5.4.2 Measurement Environment Setup...................79
5.4.3 Experiment Results..............................79
Chapter 6 A Wide-Range and Fast Locking All-Digital Delay Lock Loop................................................86
6.1 Wide-Range and Fast Locking All-Digital Delay Locked Loop..............................................86
6.1.1 Proposed WRADDLL Architecture...................86
6.1.2 Timing and Operation Analysis...................88
6.2 Implementation of WRADDLL.......................93
6.2.1 Coarse Digital-Controlled Delay Line............93
6.2.2 Error Generator and Time to Digital Converter...94
6.2.3 Frequency Selector..............................94
6.2.4 Fine Tune Structure.............................95
6.3 Simulation Results..............................95
6.3.1 System Simulation Results.......................95
6.3.2 Monte Carlo Analysis............................97
6.4 Measurement Environment Setup and Experiment Results..................................................98
6.4.1 Concept.........................................98
6.4.2 Measurement Environment Setup...................99
6.4.3 Experiment Results..............................99
Chapter 7 Conclusions and Future Works...................106
7.1 Conclusions....................................106
7.2 Future Works...................................109
References..............................................110
Publication List........................................117
Journal.................................................117
Conference..............................................118

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2011-7-15

推文