| 摘要(英) |
In order to reduce the simulation time of analog circuits, the simulation model needed to be raised to higher abstract level. Therefore, the ideal behavioral model of a switched-capacitor integrator has been developed by using Verilog-A Hardware Description Language in this thesis.
In our ideal model, the behavior of integrator in time-domain has been described more carefully to make our model more close to the real circuits. In the case of non-ideal effect in the integrator, not only the DC Gain, DC Level Offset, External Slew Rate and Switch Thermal Noise have been considered. We also consider several important non-ideal effects like Settling Time of integrator, Operational Amplifier Noise and Supply Voltage Variation. We build a standard extraction by using bottom-up method to extract those non-ideal parameters. After annotating those non-ideal parameters in to our ideal model, then the behavior of our developed model can be more close to real circuits.
In this thesis, we use a second-order sigma-delta modulator, which includes two switched-capacitor integrators, to verify our developed model. According to the experimental results, the behavior of our model can perform more close to the real circuits in time-domain. And due to the accurate time-domain behavior of our developed model, the behavior in frequency-domain can also fit the exact behavior of real circuits. The most important thing is that using our developed model can greatly reduce the simulation time instead of the traditional simulation methods. |
| 參考文獻 |
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