博碩士論文 945201009 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:13 、訪客IP:44.200.194.255
姓名 廖欽寬(Chin-Kuang Lian)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 對於長解碼長度可降低其記憶體使用的低密度同位檢查碼解碼器設計
(A Partially Parallel Low-Density Parity Check Code Decoder with Reduced Memory for Long Code-Length)
相關論文
★ 用於類比/混和訊號積體電路可靠度增強的加壓測試★ 應用於電容陣列區塊之維持比值良率的通道繞線法
★ 即時的SIFT特徵點擷取之低記憶體硬體設計★ 即時的人臉偵測與人臉辨識之門禁系統
★ 具即時自動跟隨功能之自走車★ 應用於多導程心電訊號之無損壓縮演算法與實現
★ 離線自定義語音語者喚醒詞系統與嵌入式開發實現★ 晶圓圖缺陷分類與嵌入式系統實現
★ 語音密集連接卷積網路應用於小尺寸關鍵詞偵測★ G2LGAN: 對不平衡資料集進行資料擴增應用於晶圓圖缺陷分類
★ 補償無乘法數位濾波器有限精準度之演算法設計技巧★ 可規劃式維特比解碼器之設計與實現
★ 以擴展基本角度CORDIC為基礎之低成本向量旋轉器矽智產設計★ JPEG2000靜態影像編碼系統之分析與架構設計
★ 適用於通訊系統之低功率渦輪碼解碼器★ 應用於多媒體通訊之平台式設計
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 由於低密度同位檢查碼 (LDPC) 的編碼增益接近向農 (Shannon) 極限,而且在解碼程序上,LDPC擁有低複雜度的特性,所以在近年來受到廣泛的討論。也因此LDPC被許多標準認定為是相當傑出的錯誤更正碼進而被使用在很多不同的通訊應用上,例如:數位衛星電視(DVB-S2), 無線區域網路MIMO-WLAN (802.11n), 無線都會網路WMAN (802.16e)和行動寬頻無線接取技術(MBWA) (802.20)等等。在演算法上,LDPC解碼是使用訊息傳送的演算法,使用這樣的演算法在硬體實現上必須使用記憶體來儲存交換的訊息,而所需要的記憶體量跟同位元矩陣(H matrix)中所包含1的數量有關。換句話說,當同位元矩陣的長度越長或矩陣的大小越大則所需要的記憶體量就會越多。在此篇論文,我們提出了一種方法跟架構去減少記憶體的儲存量,而且這樣的一個方式在同位元矩陣相當大的應用—DVB-S2會有相當多的記憶體節省量。
摘要(英) In recent years, low-density parity-check (LDPC) codes have attracted a lot of attention due to the near Shannon limit coding gains when iteratively decoded. Thus, the LDPC codes have been well recognized as an excellent error correction coding scheme for many digital communication systems, such as the next generation digital video broadcasting (DVB-S2), MIMO-WLAN (802.11n), WMAN (802.16e), mobile broadband wireless access (MBWA) (802.20) systems, and etc. Based on the message-passing algorithm, the LDPC decoder uses memories to store intermediate data between bit nodes and check nodes. In fact, the quantity of the stored data is related to the non-zero entries in H matrix. In other words, the memory size required by the LDPC decoder with the partially parallel architectures may significantly increase for large code length LDPC codes. In this thesis, we present an alternative approach which significantly reduces the memory size requirement and the salient feature of memory size reduction becomes significance particular for DVB-S2 applications.
關鍵字(中) ★ 低密度同位檢查碼
★ 解碼器
關鍵字(英) ★ LDPC Decoder
★ Parallel
★ Long Code-Length
論文目次 Abstract i
Content iv
List ofFigures vi
List of Tables viii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 LDPC Decoding Algorithms 3
2.1 Concept of LDPC 4
2.2 Message Passing Algorithm 5
2.3 LDPC Decoding Algorithms 7
2.3.1 Sum-Product Algorithm 7
2.3.2 Log-Likelihood Ratio for Sum-Product Algorithm 10
2.3.3 Min-Sum Algorithm 12
Chapter 3 Architectures of LDPC Decoder 15
3.1 Architectures of LDPC Decoder 16
3.1.1 Serial Architecture 16
3.1.2 Fully Parallel Architecture 17
3.1.3 Partially Parallel Architecture 18
3.1.4 Discussion 20
3.2 CNFU and BNFU 21
3.2.1 LLR-SPA 22
3.2.2 Modify Min-Sum 24
3.2.3 Discussion 25
3.3 Irregular LDPC Decoder 25
Chapter 4 Architecture Design and Circuit implementation 31
4.1 Decoder Design 32
4.1.1 Modify Min-Sum Algorithm 32
4.1.2 Architecture Overview 35
4.1.3 Value Generator Unit (VG) 37
4.1.4 Sum Generator Unit for column operation (SGU) 38
4.1.5 Minimum generator unit for row operation 39
4.1.6 Memory arrangement 41
4.1.7 Data Retrieval Scheme 42
4.1.8 Overall Architecture 44
4.1.9 Proposed Architecture for irregular LDPC 46
4.2 Experimental Results 48
Chapter 5 Conclusion 52
5.1 Summary and Conclusion 52
5.2 Future Work 54
Reference 55
參考文獻 [1]R. G. Gallager, “Low-density parity-check codes,” IRE Trans. on Information Theory, vol. IT-8, pp. 21-28, Jan. 1962.
[2]R. G. Gallager, Low-Density Parity-Check Codes, Cambridge, MA:MIT press, 1963.
[3]D. J. C. Mackay and R .M. Neal, “Near Shannon limit performance of low-density parity-check codes” Electronics. Letters., vol. 32, pp. 1645-1646, Aug. 1996.
[4]C. Berrou, A. Glavieux and P. Thitimajshima, “Near Shannon limit error-correcting codes and decoding,” Proc. International Conference on Communication, pp. 1064-1070, May 1993.
[5]J. L. Fan, Constrained Coding and Soft Iterative Decoding, Netherlands: Kluwer Academic, 2001.
[6]G. D. Forney, “Codes on graphs: Normal realizations,” IEEE Trans. on Information Theory, vol. 47, no. 2, pp. 520-548, Feb. 2001
[7]F. R. Kschischang, B. J. Frey and H. A. Loeliger, “Factor graphs and the sum-product algorithm,” IEEE Trans. on Information Theory, vol. 47, no.2, pp. 498-519, Feb.2001.
[8]A. Anastasopoulos, “A comparison between the sum-product and min-sum iterative detection algorithms based on density evolution,” Proc. IEEE GLOBECOM’01, vol. 2, pp. 1021-1025, May 1993.
[9]X. Y. Hu, E. Eleftheriou, D. M. Arnold and A. Dholakia, “Efficient implementation of the sum-product algorithm for decoding LDPC codes,” Proc. IEEE GLOBECOM’01, vol. 2, pp.25-29, Nov. 2001.
[10]J. Chen and M. P. C. Fossorier, “Near optimum universal belief propagation based decoding of low-density parity check codes,” IEEE. Trans. on Communication, vol. 50, pp. 406-414, Mar. 2002.
[11]J. Heo and K. M. Chugg, “Optimization of scaling soft information in iterative decoding via density evolution methods,” IEEE. Trans. on Communication, vol. 6, pp. 957-961, Jun. 2005.
[12]Z. Wang, Y. Chen and K.K Parhi, ”Area efficient decoding of quasi-cyclic low density parity check codes,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Volume 5, pp: 49-52, May 2004.
[13]Y. Zhang, Z. Wang and K. K. Parhi, ”Efficient high-speed quasicyclic LDPC decoder architecture,” Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, Volume 1, pp: 540 – 544. Nov., 2004.
[14]Z Wang and O. W. Jia, ”Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes,” Proc. IEEE International Symposium on Circuits and Systems, pp:5786 – 5789, May 2005
[15]A. J. Blanksby and C. J. Howland,”A 690-mW 1-Gbs 1024-b rate12 low-density parity-check code decoder,” IEEE Journal of Solid-State Circuits, Volume 37, Issue 3, pp:404 – 412, March 2002.
[16]K. K. Gunnam, G. S. Choi and M. B. Yeary, ”A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes,” Proc. 20th International Conference on VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems, pp:738 – 743, Jan. 2007.
[17]E. Yeo, P. Pakzad, B. Nikolic and V. Anantharam, “VLSI architectures for iterative decoders in magnetic recording channels,” IEEE Trans. on Magnetics, vol. 37, pp. 748-755, Mar. 2001.
[18]Y. Chen and D. Hocevar, ”A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder” IEEE GLOBECOM '03. Volume 1,1-5 pp:113 – 117, Dec. 2003.
[19]Y. Pei, L. Yin and J. Lu, ”Design of irregular LDPC codec on a single chip FPGA,” Proc. IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication, Volume 1, pp:221 – 224, 2004.
[20]Z. Cui and Z. Wang, ”A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA,” Proc. IEEE International Symposium on Circuits and Systems, pp:21-24, May 2006.
[21]Z. Wang and Z. Cui, ”Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Volume 15, Issue 1, pp:104 – 114, ,Jan. 2007.
[22]J. Sha, M. Gao, Z. Zhang, L. li and Z. Wang, ”Efficient Decoder Implementation for QC-LDPC Codes,” Proc. International Conference on Communications, Circuits and Systems Proceedings, Volume 4, pp:2498 – 2502, June 2006.
[23]T. Ishikawa, K. Shimizu, T. Ikenaga and S. Goto, ”High-Throughput LDPC Decoder for Long Code-Length,” Proc. International Symposium on VLSI Design, Automation and Test, pp:1 – 4, April 2006.
[24]M. Karkooti and J. R. Cavallaro, ”Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding,” Proc. ational Conference on nformation Technology: Coding and Computing, Volume 1, pp:579 - 585 Vol.1, 2004.
[25]T Zhang and K.K. Parhi., ”A 54 Mbps (3,6)-regular FPGA LDPC decoder” Proc. IEEE Workshop on Processing Systems, pp:127 – 132, Oct. 2002
[26]P. Bhagawat, M. Uppal and G. Choi, “FPGA Based Implementation of Decoder for Array Low-Density Parity-Check Codes,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Volume 5, pp: 29 - 32 Vol. 5, March 2005.
[27]K. Shimizu, T. Ishikawa, N. Togawa, T. Ikenaga and S. Goto, ”Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm,” Proc. IEEE International Conference Computer Design: VLSI in Computers and Processors, pp: 503 – 510, Oct. 2005.
[28]I. C. Park and S. H. Kang, ”Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation,” Proc. IEEE International Symposium Circuits and Systems, pp:5778 - 5781 Vol. 6, May 2005.
[29]S. H. Kang and I. C. Park, ”Loosely coupled memory-based decoding architecture for low density parity check codes,” IEEE Trans on Crcuits and Systems I: Fundamental Theory and Applications, Volume 53, Issue 5, pp:1045 – 1056, May 2006.
[30]G. Masera, F. Quaglio and F. Vacca, ”Implementation of a Flexible LDPC Decoder,” IEEE Trans. on Circuits and Systems II: Express Briefs : Accepted for publication Volume PP, Issue 99, pp:1 – 1, 2007.
[31]L. Yang, M. Shen, H. Liu and C.J.R Shi, “An FPGA implementation of low-density parity-check code decoder with multi-rate capability,” Proc. Asia and South Pacific Design Automation Conference, Volume 2, pp:760 - 763 Vol. 2, Jan. 2005.
[32]M. Karkooti, P. Radosavljevic and J. R. Cavallaro, “Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation,” Proc. International Conference Application-specific Systems, Architectures and Processors, pp: 360 – 367, Sept. 2006.
[33]M. Mansour and N. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE Journal of Solid- State Circuits, vol. 41, no.3, pp. 684- 698, March 2006.
[34]T. Zhang and K.K. Parhi, ”Joint (3,k)-regular LDPC code and decoder/encoder design,” IEEE Trans. on Signal Processing, [see also IEEE Trans. on Acoustics, Speech, and Signal Processing,] Volume 52, Issue 4, pp:1065 – 1079, April 2004.
[35] A. Roumy, S. Guemghar, G. Caire and S. Verdu, ”Design methods for irregular repeat-accumulate codes,” IEEE Trans. on Information Theory, Volume 50, Issue 8, pp:1711 – 1727, Aug. 2004.
[36]Digital Video Broadcasting (DVB) second generation system for Broadcasting, Interactive Services, News Gathering and Other Broadband satellite applications, ETSI Std. En 302 307,2005.
[37]F. Kienle, T. Brack, and N. Wehn, “A synthesizable IP core for DVB-S2 LDPC code decoding,” Proc. Design, Automation and Test in Europe, pp: 100 – 105, 2005.
[38]P. Urard, E. Yeo, L. Paumier,P. Georgelin, T. Michel, V. Lebars, E. Lantreibecq and B. Gupta ” A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes,” Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp: 446 – 609, Feb. 2005.
指導教授 魏慶隆、蔡宗漢
(Chin-Long Wey、Tsung-Han Tsai)
審核日期 2007-7-17
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明