可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計

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姓名

楊耀先(Yao-Xian Yang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計
(Design of Self-Testable and Cost-Efficient Memory-Based FFT Processors)

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摘要(中)

快速傅利葉轉換處理器已被廣泛的使用在各種數位領域中，如通訊系統和數位訊號處理器等等。記憶體式快速傅利葉轉換處理器是針對低成本應用所衍生出來一種熱門的設計方式，本論文將針對此技術提出一具成本效益之記憶體式快速傅利葉轉換處理器。跟現存處理器的相異之處在於所提出的處理器利用單埠記憶體做為資料存取，進而取代典型記憶體式傅利葉處理器利用雙埠記憶體的設計方式。此提出之方法將能大大的降低處理器在面積上之消耗，此外單埠記憶體的使用無論在功率消耗或是測試時間上，比起雙埠記憶體的使用將能有效的降低。
另一方面，本論文也針對記憶體式之傅利葉轉換處理器提出一內建自我測試的方法，此內建測試能夠提供邏輯和記憶體上的電路測試。與現存的方法相比，我們的內建測試設計有較低之面積需求和較低延遲之衝擊。
我們利用提出的快速傅利葉的架構搭配內建的測試設計，以256/1024點數來實現此可自我測試之記憶體式快速傅利葉轉換處理器。此實驗使用TSMC 0.18um standard cell library來進行模擬，整個可自我測試之傅利葉處理器的面積只需1.72x1.72 mm^2。

摘要(英)

Fast-Fourier transform (FFT) processor is widely used in digital systems, such as communication, digital signal processing (DSP), etc. The memory-based FFT processor is one popular design style for low-cost applications. This thesis proposes a cost-efficient memory-based FFT processor. Differing from the existing memory-based FFT processors, the proposed memory-based FFT processor uses single-port RAMs for data buffering instead of using two-port RAMs. Therefore, the area of the proposed memory-based FFT processor can drastically be reduced. Also, the power consumption and testing cost of single-port RAMs are much less than those of two-port RAMs.
On the other hand, this thesis also proposes a built-in self-test scheme (BIST) for memory-based FFT processors. The BIST can support the testing of logic circuits and RAMs. Comparing with the existing approach, our BIST scheme has the advantages of low area cost and small delay penalty.
We realized a 256/1024-point self-testable memory-based FFT processor using the proposed FFT architecture and BIST scheme. The area cost of the self-testable memory-based FFT processor is only about 1.72x1.72 mm^2, where TSMC 0.18 um standard cell library is used.

關鍵字(中)

★ 內建自我測試電路
★ 記憶體式快速傅利葉轉換

關鍵字(英)

★ BIST
★ Memory-Based FFT

論文目次

Chapter 1 Introduction..1
Chapter 2 Overview of Memory-Based FFT Processors..4
2.1 FFT algorithm..4
2.1.1 Discrete Fourier Transform..4
2.1.2 Decimation-In-Frequency Radix-2 FFT Algorithm..5
2.1.3 Decimation-In-Time Radix-2 FFT Algorithm..9
2.1.4 Radix-4 FFT Algorithm..10
2.2 Various Memory-Based FFT Processors..13
2.2.1 FFT Processors with 1.5N-bit Two-Port RAMs..13
2.2.2 FFT Processors with 2.5N-bit Two-Port RAMs..15
2.2.3 FFT Processors with 1.25N-bit Two-Port RAMs.16
2.2.4 FFT Processors with 1N-bit Two-Port (Single-Port) RAMs..18
Chapter 3 Proposed Memory-Based FFT Processors..20
3.1 Architecture of the Proposed SPMFFT Processor.20
3.2 The Controller of SPMFFT Processor..26
3.2.1 Generation of RAM Control Signals..26
3.2.2 Control Signals for Multiplexers and Adders..34
3.2.3 Control Signals for the ROM..38
3.3.4 Design-for-Reconfigurability Control..40
3.3 Analysis and Comparison Results..40
Chapter 4 A Built-In Self-Test Scheme for Memory-Based
FFT Processors..44
4.1 Introduction..44
4.2 Previous Work..44
4.3 BIST Scheme..47
4.3.1 Integration of the BIST Scheme and the SPMFFT Processor ..49
4.3.2 The BIST Structure..51
4.4 Analysis and Comparison..58
Chapter 5 Test Chip of a 256/1024-point SPMFFT Processor.61
5.1 Design Flow..61
5.2 Verification..62
5.3 Synthesis Results..64
5.3.1 Gate-Level Simulation..65
5.3.2 Power Analysis..69
5.4 Placement and Routing..69
5.5 Post-Layout Simulation..71
5.6 Comparison Results..73
Chapter 6 Conclusions and Future Works..76
Reference ..77

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指導教授

李進福(Jin-Fu Li)

審核日期

2007-7-25

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