馴變者：在實體實現上決定最佳佈局擺放位置的一個異質平台

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何秋億(Chio-Yi Ho) 查詢紙本館藏

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電機工程學系

論文名稱

馴變者：在實體實現上決定最佳佈局擺放位置的一個異質平台
(VariTamer: A Heterogeneous Platform for Deciding the Best Layout Placement in Physical Implementation)

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摘要(中)

隨著電晶體尺寸下降，且製程微縮至90 奈米以下，會帶來較劇烈的參數變動。在未來SoC 設計時，類比EDA 的需求越來越重要。在晶圓廠製造過程中，因為經過相同的物理程序，所以電晶體間的參數變動會有某種程度的關聯性，此關聯性可用來改善良率。在本論文中，建構一個類比電路設計自動化異質平台，以MATLAB所架構，並整合了數種不同環境，包含了電路模擬器(Hspice), 工作站作業系統連線通訊協定(SSH)與檔案傳輸協定(Ftp)，並以一個雙級運算放大器為範例，根據兩步驟的最佳化程序，考量空間相關性來決定佈局時電晶體最佳的佈局擺放位置。由模擬結果得知，本平台可找到對不同規格之最佳排法，有效地提升良率。

摘要(英)

While MOS transistors continuously scale down in technologies below 90 nano-meter, they bring along larger parameter variability. Analog EDA is needed increasingly
important in future SoC design. The parameter variation of all transistors should have certain correlations during IC manufacturing process because all of them are made from the common physical process and the correlations can be used for yield improvement. In this thesis, a heterogeneous platform of analog EDA, which is implemented on MATLAB, is provided by integration of several environments including the circuit simulator (Hspice), communication protocol via workstation OS (SSH) and file transfer protocol (Ftp). A two-stage OpAmp is used as an example circuit to demonstrate the performance of a proposed two-step optimization procedure for determination of best layout placement by spatial correlation. By the simulation results, the best layout placements with respect to the corresponding parameters can be given to improve the effective yield.

關鍵字(中)

★ 異質平台
★ 佈局擺放
★ 製程變動
★ 空間相關性

關鍵字(英)

★ spatial correlation
★ heterogeneous platform
★ layout placement
★ process variation

論文目次

Chapter 1 Introduction 1
1.1 Process Variation Classification 3
1.2 Mismatch 5
Chapter 2 Basic Definition of Statistics 6
Chapter 3 Spatial Correlation 10
Chapter 4 Analysis Flow 13
4.1 Proposed Analysis Procedure 13
4.2 Working Flow 14
Chapter 5 Design of Experiments 16
5.1 Design of a Two-Stage Operational Amplifier 16
5.2 Mismatch Parameters 19
5.3 Two-Step Placement 21
Chapter 6 GUI analyzer 22
Chapter 7 Experiment Results 26
7.1 Box-stacking 26
7.1.1 Input offset voltage 26
7.1.2 SR+ 27
7.1.3 SR- 28
7.1.4 CMRR 29
7.1.5 PSRR 30
7.2 Performance Evaluations 32
7.3 Yield Evaluations 33
7.3.1 SR+ 33
7.3.2 CMRR 34
7.4 Better Layout Placement 35
7.5 Segmentation 37
Chapter 8 Conclusions and Future Works 40
8.1 Conclusions 40
8.2 Future Works 40
Reference 41

參考文獻

[1] S. Borkar, R. Brodersen, J. Chern, E. Naviasky, D. Saias, and C. Sodini, “Tomorrow's
analog: just dead or just different?” ACM/IEEE Design Automation Conference, 24-28
July 2006, pp. 709-710.
[2] A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, Z. Min, K. Gala, and R. Panda,
“Statistical delay computation considering spatial correlations,” Asia and South Pacific
Design Automation Conference, 21-24 Jan. 2003, pp. 271-276.
[3] X. Jinjun, V. Zolotov, and H. Lei, “Robust Extraction of Spatial Correlation,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, Iss.
4, April 2007, pp. 619-631.
[4] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of
MOS transistors,” IEEE Journal of Solid-State Circuits, Vol. 24, Iss. 5, Oct 1989, pp.
1433-1439.
[5] S. G. Duvall, “Statistical circuit modeling and optimization,” 5th International Workshop
on Statistical Metrology, 2000, pp. 56-63.
[6] S. Nassif, “Modeling and analysis of manufacturing variations,” IEEE Conference on
Custom Integrated Circuits, 2001, pp. 223-228.
[7] S. Nassif, D. Boning, and N. Hakim, “The care and feeding of your statistical static timer,”
IEEE/ACM International Conference on Computer Aided Design, 7-11 Nov. 2004, pp.
138- 139.
[8] K. A. Bowman, S. G. Duvall, and J. D. Meindl, “Impact of die-to-die and within-die
parameter fluctuations on the maximum clock frequency distribution for gigascale
integration,” IEEE Journal of Solid-State Circuits, Vol. 37, Iss. 2, Feb 2002, pp. 183-190.
[9] D. J. Frank, Y. Taur, M. Ieong, and H.-S. P. Wong, “Monte Carlo Modeling of Threshold
Variation Due to Dopant Fluctuations,” Symposium on VLSI Circuits, 1999, pp. 171-172.
[10] N. Mukhopadhyay, Probability and Statistical Inference, CRC Press, 2000.
[11] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Oxford University Press,
Inc., 2002, pp. 244-341.
[12] C.S.G. Conroy, W.A. Lane, and M.A. Moran, “Statistical Design Techniques for D/A
Converters,” IEEE Journal of Solid-State Circuits, Vol. 24, Iss. 4, Aug 1989, pp.
1118-1128.
[13] S. S. Wang, EMN_RVG: An Enhanced Multivariate Normal Random Vector Generator
for Circuit Analysis, master’s thesis, Dept. Electrical Engineering, Chung-Hua University,
Hsinchu, 2001.
[14] T. Serrano-Gotarredona and B. Linares-Barranco, “A New Five-Parameter MOS
Transistor Mismatch Model,” IEEE Electron Device Letters, Vol. 21, Iss. 1, Jan 2000, pp.
37-39.
[15] T. Serrano-Gotarredona and B. Linares-Barranco, "A 5-Parameters Mismatch Model for
Short Channel MOS Transistors," European Solid State Circuits Conference, 1999, pp.
440-443.
[16] Y.J. Dai, Correlation Analysis for CMOS Transistor Mismatch and Circuit Performance
Estimation, master’s thesis, Dept. Electrical Engineering, Chung-Hua University, Hsinchu,
2003.

指導教授

陳竹一(Jwu-E Chen)

審核日期

2007-7-16

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