設計具有硬體效益的類比-數位三角積分調變器

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姓名

江宜倫(Yi-Lun Chiang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

設計具有硬體效益的類比-數位三角積分調變器
(Design of a Hardware-Effective Delta-Sigma A/D Modulator)

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摘要(中)

本論文提出一個新的高階三角積分調變器的架構，用以達成效能提升與節省硬體的效果。與傳統架構相比，本架構使用一迴授機制，使得調變器的等效階數在不增加積分器個數的條件下，能夠往上提升，因此其訊雜比優於傳統架構。此一架構並不需要太多額外的電路與功耗，因此能有效提升其效能性質 (Figure of Merit, FOM)。
本論文並且展現基於此一架構所設計的一個等效兩階類比/數位三角積分調變器電路。該電路可以使用於音頻應用上，並且以可攜帶性為考量。其操作電壓為1.5V~1.2V，適用於電池供應電源。電路本身以全差動交換式電容電路實現。在訊號頻寬為20KHz，超取樣率為64 的情況下，以TSMC 0.18μm製程作模擬，此電路的訊雜比較傳統一階架構高出約20dB。

摘要(英)

A high-order architecture of delta-sigma A/D modulator is proposed in this thesis. The proposed architecture, based on conventional structure and using an extra feedback circuitry, can increase the equivalent order of the modulator. Therefore, the figure of merits (FOM) of the proposed architecture increases effectively without spending too much hardware.
Based on the proposed architecture, an equivalent second-order delta-sigma analog-to-digital modulator is designed and presented in the thesis. The designed circuit is aimed for the portable audio application and is operated on a battery power source ranging from 1.2V to 1.5V. This design is implemented with fully differential switch-capacitor circuitry. With a signal bandwidth of 20kHz, an oversampling ration of 64 times, the peak signal-to-noise ratio of the proposed architecture is 20dB superior than the conventional first-order modulator, by using the TSMC 0.18μm CMOS process for the circuit simulation.

關鍵字(中)

★ 三角積分

關鍵字(英)

★ delta-sigma

論文目次

摘要 i
英文摘要 ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 x
第一章介紹 1
1-1 動機 3
1-2論文組織 5
第二章類比數位轉換器與三角積分調變原理 6
2-1 類比數位轉換器種類 6
2-2 類比數位轉換器原理 9
2-2-1 量化誤差 10
2-3 類比數位轉換器效能頻估 12
2-3-1 解析度 12
2-3-2 超取樣率 13
2-3-3 尼奎斯特速率ADC 13
2-3-4 超取樣ADC 14
2-3-5 特性值 15
2-3-6 ΔΣ ADC 16
2-4 ΔΣ調變器 17
2-4-1 ΔΣ調變器由來 17
2-4-2 ΔΣ 調變器 19
2-4-3 線性模型 20
2-4-4 低階ΔΣ調變器 21
第三章高階ΔΣ調變器的架構 24
3-1 高階ΔΣ架構 24
3-1-1 單迴路式架構 25
3-1-2 串疊式架構 29
3-1-3 總結 31
3-1-4 低失真型架構 32
3-1-5 DAC誤差消除架構 33
3-2 新提出的架構 34
3-2-1 架構 34
3-2-2 架構模擬 37
第四章電路實現 39
4-1 設計規格 39
4-1-1 應用 39
4-1-2 工作電壓的考量 39
4-2 電路評估 41
4-2-1 電容評估 42
4-2-2 開關電路 43
4-2-3 放大器考量 49
4-3 電路方塊 57
4-3-1 非重疊時脈訊號產生器 57
4-3-2 延遲電路 59
4-3-3 比較器 61
4-3-4 運算放大器 63
4-3-5 調變器電路 65
4-3-6 模擬結果 69
第五章結論 71
參考文獻 72

參考文獻

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指導教授

陳竹一(Jwu-E Chen)

審核日期

2008-1-1

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