博碩士論文 945201018 詳細資訊




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姓名 曾培凱(Pei-kai Tseng)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 5Gbps 3 倍超取樣眼圖追蹤式時脈資料回復電路
(5Gbps 3X Over-Sampling Eye-Tracking Clock And Data Recovery Circuit)
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摘要(中) 隨著製程技術的進步及運算處理速度的提升,傳送接收系統應用在高速上是未來的趨勢,例如應用在乙太網路及光纖網路上規格,如10G Base- LX4、OC-192、OC-768…等。著重在有線或是匯流排上的應用有PCI-EXPRESS、USB2.0、IEEE1394、SERIAL-ATA…等系統,在此系統當中所傳送的資料速度多為Gb/s的等級。高速資料傳送上,有更多的困難需要克服。如雜訊的處理,時脈產生器如何產生高速時脈…等等的問題。本論文採用三倍超取樣眼圖追鎖的技術應用在接收端的時脈資料回復電路上,並以應用PCI-Express II的規格為目標。
本論文是應用在5Gb/s的傳送系統的資料接收端的電路上,達到一個高速5Gb/s串列資料。利用鎖相迴路(PLL)作為系統上的時脈產生器,產生5GHz時脈對於輸入的資料作取樣的動作。系統當中需要切割出微小的時脈延遲來調整取樣時脈的相位,採用相位內插的電路利用電流切割方式,切割出6.25ps左右的延遲相位,以達到系統上所規定的頻寬。三倍超取樣的方式可以達到較小的靜態相位誤差,四倍或五倍超取樣的方式複雜度又太大。
在整體電路實現上,我們採用0.13-um製程,1.2-V的供應電源來實現接收端的電路。
摘要(英) With the progress in the CMOS process technologies and the operating speed of the processor, high speed links in the transmitter and receiver system are the future tendency . For example, 10Gbase-LX4, OC-192, OC-768 are applied in Gigabit Ethernet and Fiber Channel; PCI-EXPRESS, USB2.0, IEEE1394 and SERIAL-ATA are used in wire or bus serial links. Most of the systems operate at the data rate attending to the level of Gb/s. With the increase of operation frequency, the system design becomes more difficult. These difficulties include noise handling and the generation of the sampling clock at high frequency in receiver side, etc. The thesis adopts 3X over-sampling-eye-tracking techniques in the receiver circuit and tries fit the corresponding specification of PCI- Express II.
We designed a receiver circuit which is used in the one serial in data with 5Gb/s and retimed them to a serial 5Gb/sdata. PLL circuit is used as the clock generation circuit and the output clock signals of PLL are used to sample the input data. The small phase delay circuit is implemented by phase interpolator delay to make approximate 6.25ps delay and to tune the phase of sampling clock. A small phase delay is required because of the specification of CDR bandwidth. The reason we adopted the 3X over-sampling is that 2X over-sampling system has larger static phase error and circuit in 4X or 5X is too complex.
The receiver system in the thesis is implemented with a 0.13-um CMOS technology with a 1.2V supply power.
關鍵字(中) ★ 超取樣
★ 眼圖追踨
★ 時脈資料回復電路
關鍵字(英) ★ over-sampling
★ eye-tracking
★ clock and data recovery
論文目次 摘 要 I
Abstract II
目錄 III
圖目錄 VI
表目錄 X
Chapter 1 1
簡介 1
1.1動機 1
1.2論文架構 2
Chapter 2 3
時脈回復電路的背景 3
2.1簡介 3
2.2串列連接層(serial link )與平行連接層(Parallel link ) 4
2.3 時脈回復電路的架構 5
2.3.1 鎖相迴路式的時脈資料回復電路 6
2.3.1.1 壓控振盪器(VCO)的抖動表現 6
2.3.1.2振盪器的頻率 6
2.3.1.3 有參考時脈及無參考時脈的時脈回復電路 7
2.3.2 超取樣式的時脈資料回復電路 10
2.3.3 相位內插式的時脈資料回復電路 11
Chapter 3 12
抖動分析 12
3.1前言 12
3.2抖動簡介 12
3.3 通道的雜訊來源 14
3.3.1 連接層中的通道的衰減與信號自身的干擾(ISI Inter-Symbol Interference ) 14
3.3.1.1 信號擴散效應 15
3.3.1.2 信號反射效應 15
3.3.2 電壓源的雜訊 16
3.4抖動容忍度(Jitter tolerance) 16
3.5抖動轉移函數(Jitter Transfer Function ) 17
3.6抖動峰值(Jitter Peaking) 18
3.7抖動產生量(Jitter Generation) 18
Chapter 4 19
時脈資料回復電路架構 19
4.1時脈資料回復電路的架構 19
4.1.1時脈資料回復電路的規格 19
4.1.2時脈資料回復電路的架構 20
4.1.2.1傳統式三倍超取樣時脈資料回復電路 20
4.1.2.2改良式三倍超取樣時脈資料回復電路 21
4.2 在時脈資料回復電路的設計 23
4.2.1鎖相迴路的設計 23
4.2.1.1 相位頻率偵測電路(Phase Frequency Detector) 23
4.2.1.2 充電電流泵(Charge pump circuit) 24
4.2.1.3 迴路濾波器(Loop filter) 24
4.2.1.4 電壓控製振盪器(Voltage Control Oscillator) 25
4.2.1.5 除頻器(Divider) 25
4.2.1.6 PLL的線性度分析 25
4.2.2資料回復電路的設計架構 29
4.2.2.1 三倍超取樣的資料回復電路之操作方式 29
4.2.2.2 抖動容忍度頻寬分析 32
4.2.2.3 抖動轉移函數頻寬分析 34
4.2.2.4相位內插電路 35
4.2.2.4.1傳統相位內插電路Ⅰ 35
4.2.2.4.2傳統相位內插電路Ⅰ 36
4.2.2.4.3相位內插電路 37
4.3 三倍超取樣電路時序圖 37
Chapter 5 39
時脈資料回復電路設計 39
5.1設計流程 39
5.2鎖相迴路(PLL Phase Locked Loop) 40
5.2.1 相位頻率偵測器(Phase Frequency Detector ) 40
5.2.2 充電電流泵(Charge Pump ) 42
5.2.3 壓控振盪器(Voltage Control Oscillator ) 43
5.2.4 除頻電路(Divider) 44
5.2.5 電流式邏輯雙端轉單端電路(CML Differential to Single circuit) 47
5.2.6 責任週期位移補償電路(Duty Cycle Deskew) 48
5.3資料回復電路 50
5.3.1 相位比較電路(Phase Comparator) 51
5.3.1.1 決策框架電路 51
5.3.1.2 數位相位偵測器(Bang-Bang! Phase 52
5.3.2 多數投票機制電路 52
5.3.3 相位旋轉電路(Phase Rotate) 55
5.3.6 輸出輸入驅動電路 59
5.3.6.1 資料及時脈輸入驅動電路 59
5.3.6.2 資料及時脈輸出驅動電路 61
5.4資料時脈回復電路 62
5.4.1時脈資料回復電路模擬 62
5.4.2時脈回復電路佈局 66
Chapter 6 68
時脈資料回復電路量測結果 68
6.1 前言 68
6.2 量測環境 68
6.3 5Gbps串列輸入及5Gbps串列輸出時脈回復電路量測結果 69
6.3.1 鎖相迴路量測結果 70
6.3.2 時脈資料回復電路量測結果 73
Chapter 7 78
結論 78
7.1 結論 78
7.2未來電路的改進方向 79
References 80
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指導教授 鄭國興(Kuo-Hsing Cheng) 審核日期 2007-11-26
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