以脈衝靈敏函數分析壓控振盪器之相位雜訊特性與K頻段差動低雜訊放大器之研製

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梁可駿(Keko-chun Liang) 查詢紙本館藏

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電機工程學系

論文名稱

以脈衝靈敏函數分析壓控振盪器之相位雜訊特性與K頻段差動低雜訊放大器之研製
(Impulse Sensitivity Function Analysis for Phase Noise Characteristic of Voltage Controlled Oscillator and Implementation of K-band Differential Low Noise Amplifier)

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摘要(中)

本論文的內容為壓控振盪器相位雜訊生成機制之探討與低雜訊放大器之實作。在相位雜訊探討的部分，是以時變系統的觀點分析振盪電路中各雜訊源對相位雜訊的影響，並且以實作的量測結果驗證本論文對相位雜訊的論述。使用TSMC CMOS 0.18-μm 製程實現的振盪電路包括(1)互補式交錯耦合壓控振盪器，振盪中心頻率為5.2 GHz，可調頻率範圍633 MHz，偏移主頻1 MHz 之相位雜訊為-120.2 dBc/Hz，優化指數(FOM)為-185.3 dBc/Hz；(2)雜訊平移考畢茲(Colpitts)壓控振盪器，振盪中心頻率為12.6 GHz，可調頻率範圍227 MHz，偏移主頻1 MHz 之相位雜訊為-110.3 dBc/Hz，優化指數(FOM)為-182.74 dBc/Hz；(3)低功率消耗雙變壓器耦合壓控振盪器，振盪中心頻率為12.8 GHz，可調頻率範圍136 MHz，偏移主頻1MHz 之相位雜訊為-97.08 dBc/Hz，功率消耗為0.6 mW，優化指數為-181.53 dBc/Hz 。
隨著越來越多的無線傳輸應用，現今對大量資料傳輸系統的需求已經變的更加迫切，使得我們需要更高的資料傳輸速率系統規範，因此在通訊系統規格也將載波頻率提升換取更大的頻寬，其中一個例子為K-頻段802.16 WMAN 的系統規格，因此在本論文中實現K-頻段的低雜訊放大器，並運用變壓器負回授的方式來中和閘極與汲極間電容的效應，使得在低頻的最佳雜訊設計方式在K-頻段也可適用。使用TSMC CMOS 0.18-μm 製程實現的低雜訊放大器包括(1)變壓器回授的三級低雜訊放大器，在26 GHz 有最大增益約為9.2 dB，雜訊指數為6.9dB，IIP3 及P1dB 分別為-2 dBm 及-11 dBm，功率消耗為 64 mW；(2) 變壓器回授的三級低雜訊放大器，在25.8 GHz 有最大增益約為10 dB，雜訊指數為4.84dB，IIP3 及P1dB 分別為-5 dBm 及-17.8 dBm，功率消耗為 25.8 mW。

摘要(英)

The content of this thesis is about phase noise mechanism in voltage controlledoscillator (VCO) and implementation of K-band low noise amplifier (LNA). Thetime-varying concept is used to analyze the phase noise caused by various noisesources in the circuits. The measurement results of the implemented VCO ensure thevalidity of the mentioned notion in this thesis. TSMC 0.18-μm CMOS technology isadopted to implement the following circuits; (1) Complemently cross couple VCO.The oscillation frequency is 5.2 GHz, tuning range is 633 MHz, phase noise is -120.2dBc/Hz at 1MHz offset, and -185.3 dBc/Hz of Figure-of-Merit (FOM); (2) Thesecond circuit is a noise-shifting Colpitts VCO. The oscillation frequency is 12.6 GHz,tuning range is 227 MHz, phase noise is -110.3 dBc/Hz at 1 MHz offset, and -182.74dBc/Hz of FOM; (3) The third circuit is a tripilar coupling VCO. The oscillationfrequency is 12.8 GHz, tuning range is 136 MHz, phase noise is -97.08 dBc/Hz at1MHz offset, and FOM is -181.53 dBc/Hz.
Due to the rapid development of wireless communication system, largerbandwidth and higher speed are required. In order to achieve the wide bandwidth,higher frequency communication standard become a necessary trend in recent years.For instance, the application of wireless broadband networks in IEEE 802.16 standardis wireless metropolitan area network (WMAN). Therefore, the K-band LNAs areimplemented in this thesis. In order to confirm the validity of the transistor widthoptimization method, the transformer feedback technique is employed to neutralize the gate-drain overlap capacitance. TSMC 0.18-μm CMOS technology is adopted toimplement the following LNAs; (1) A 26 GHz transformer feedback three cascadestages low noise amplifier achieved a power gain of 9.2 dB, a noise figure of 6.9 dB.The 1-dB gain compression point and the input third-order intercept point are -11dBm and -2 dBm, respectively, and total power consumption is 64 mW. (2) A 25.8GHz transformer feedback three cascade stages low noise amplifier achieved a powergain of 10 dB, 4.84 dB noise figure. The 1-dB gain compression point and the inputthird-order intercept point are -17.8 dBm and -5 dBm, respectively, and total powerconsumption is 25.8 mW.

關鍵字(中)

★ 壓控振盪器
★ 相位雜訊
★ 低雜訊放大器

關鍵字(英)

★ low noise amplifier
★ voltage controlled oscillator
★ phase noise

論文目次

中文摘要 Ⅰ
英文摘要 Ⅱ
誌謝 Ⅳ
目錄 Ⅵ
圖目錄 Ⅷ
表目錄 ⅩⅢ
第一章緒論 1
1-1 研究動機 1
1-2 研究成果 2
1-3 章節簡述 2
第二章壓控振盪器之相位雜訊分析 3
2-1相位雜訊導論 3
2-2 Lesson相位雜訊模型 5
2-3 Hajimiri 相位雜訊模型 8
2-3.1脈衝靈敏函數之特性分析 14
2-3.2雜訊調變函數之特性分析 22
2-4交錯耦合壓控振盪器之分析與實作 25
2-4.1文獻回顧 25
2-4.2交錯耦合壓控振盪器之分析 32
2-4.3 5 GHz交錯耦合壓控振盪器之實作 39
2-4.4量測結果 40
2-4.5結果討論 44
第三章應用於802.16 WMAN壓控振盪器之研製 45
3-1考畢茲振盪器簡介 45
3-1.1雜訊平移考畢茲振盪器設計原理 47
3-1.2量測結果 51
3-1.3結果討論 54
3-2變壓器回授振盪器簡介 55
3-2.1雙變壓器回授振盪器設計原理 57
3-2.2量測結果 59
3-2.3結果討論 61
第四章 K頻段差動低雜訊放大器之研製 63
4-1 K頻段差動低雜訊放大器簡介 63
4-1.1低雜訊放大器雜訊分析 63
4-1.2變壓器回授理論分析 66
4-2 K頻段差動低雜訊放大器之實作 68
4-2.1電路架構一設計原理 68
4-2.2量測結果與討論 70
4-2.3電路架構二設計原理 73
4-2.4量測結果與討論 74
第五章結論 80
5-1 結論 80
5-2 未來期許與研究方向 81
參考文獻 82

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指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2007-10-11

推文