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姓名	陳光亮(Gwong-Liang Chen)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	具有自我對準電極鍺量子點單電洞電晶體之製作與物理特性研究 (Germanium QD Single Hole Transistor with self-aligned electrodes – device fabrication and physics study)
相關論文	★ 高效能矽鍺互補型電晶體之研製 ★ 高速低功率P型矽鍺金氧半電晶體之研究 ★ 應變型矽鍺通道金氧半電晶體之研製 ★ 金屬矽化物薄膜與矽/矽鍺界面反應 之研究 ★ 矽鍺異質源/汲極結構與pn二極體之研製 ★ 矽鍺/矽異質接面動態啓始電壓金氧半電晶體之研製 ★ 應用於單電子電晶體之矽/鍺量子點研製 ★ 矽鍺/矽異質接面動態臨界電壓電晶體及矽鍺源/汲極結構之研製 ★ 選擇性氧化複晶矽鍺形成鍺量子點的光特性與光二極體研製 ★ 選擇性氧化複晶矽鍺形成鍺量子點及其在金氧半浮點電容之應用 ★ 鍺量子點共振穿隧二極體與電晶體之關鍵製程模組開發與元件特性 ★ 自對準矽奈米線金氧半場效電晶體之研製 ★ 鍺浮點記憶體之研製 ★ 利用選擇性氧化單晶矽鍺形成鍺量子點之物性及電性分析 ★ 具有自我對準下閘電極鍺量子點單電洞電晶體之研製 ★ 有機非揮發性記憶體之量測與分析
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載] 本電子論文使用權限為同意立即開放。 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中)	在此篇論文中，目的在於改善本研究室已開發前幾代單電子/電洞電晶體元件之缺點。提升元件之良率與特性，進一步探討量子傳輸效應。首先，將高摻雜物以離子佈值的方式植入複晶矽層中。在之後的高溫熱氧化形成鍺量子點的同時，摻雜物會經由擴散的方式移動至穿隧氧化物旁，形成自我對準至量子點的源∕汲極電極。用此方法可避免在定義完閘極後才離子佈值所衍生的問題，包括源∕汲極會因為閘極在電子束微影對準上之誤差而不具對稱性，導致有寄生金氧半場效電晶體的非理想效應存在。 使用上述之方法，再藉由電子束微影、氮化矽對複晶矽具有乾蝕刻高選擇比之技術，搭配製程的設計，本論文成功製作出源、汲與閘極皆能自我對準至鍺量子點地點接觸式之高溫單電子/單電洞電晶體。整體元件的製程技術含鍺量子點的形成(經完全氧化矽鍺奈米細線以形成單一顆小於10nm的鍺量子點於通道中)完全與CMOS製程相容，並且製程簡易、再現性高。在適當的偏壓下，由於庫倫阻斷的現象，使得在室溫下電壓-電流曲線即可呈現週期性震盪，且峰谷值比可高達500以上。本論文成功地提升單電子電晶體之Ion/Ioff、切換速度和降低功率消耗，並藉由非對稱穿隧氧化層之電流特性探討載子在量子點中的穿隧過程。
摘要(英)	The main purpose of this thesis is to solve the shortages of single electron/hole transistors previously fabricated in our laboratory. To improve the yield and electrical characteristics of these devices, we can get the chance to understand the quantum confinement effect in detail. First, we incorporated high concentration dopants into poly-silicon layer using ion implantation. Theses dopants will diffuse to adjacent SiO2 barrier during the subsequent oxidation process, which is used to generate a single Ge QD, to form the self-aligned source/drain electrodes to the QD. This method can avoid the misalignment issues resulting from ion implantation process after gate electrode definition. Such as the asymmetrical source/drain electrodes because of the misalignment for electron beam lithography (EBL) resulting in the non-ideal effect of parasitic MOSFET. We have successfully fabricated the high temperature Ge quantum-point-contact SETs/SHTs with self-aligned source/drain electrodes using EBL and Si3N4/Si high selectivity plasma etching technology. The key process for Ge-QD SHTs with self-aligned electrodes includes the formation of Ge QD (one Ge QD smaller than 10 nm embedded in channel after fully oxidizing the SiGe nanowire), high etching selectivity between Si3N4 to Si and SiO2 to Si, EBL patterning, and device integration. The fabricated Ge-QD SHTs display homogeneous current oscillations at room temperature owing to Coulomb blockade effect. In particular, peak-to-valley current ratio is up to 500, and the background current (as low as 10-12 A - 10-13 A) doesn’t increase with applied gate voltage. This indicated that gate-induced tunneling barrier lowering is significantly suppressed owing to the self-aligned process. This thesis successfully improve the Ion/Ioff、switching speed and power consumption. Besides, we have experimentally studied the carrier quantum transport through the Ge QD using asymmetrical tunneling barriers device.
關鍵字(中)	★ 自我對準電極 ★ 庫倫阻斷 ★ 單電子電晶體 ★ 量子點 ★ 鍺	關鍵字(英)	★ single electron transistor ★ germanium ★ Coulomb blockade ★ self-aligned electrodes ★ quantum dot
論文目次	中文摘要.................................................Ⅰ 英文摘要.................................................Ⅱ 致謝.................................................... Ⅳ 圖目錄...................................................Ⅴ 表目錄...................................................Ⅹ 第一章 簡介..............................................1 1-1 半導體的發展........................................1 1-2 單電子/電洞電晶體的發展.............................2 1-3 研究動機............................................3 1-4 單電子電晶體的應用..................................4 第二章 單電子/電洞電晶體之操作原理.......................11 2-1 基本概念...........................................11 2-2 調變VDS、固定VG...................................12 2-3 調變VG、固定VDS...................................14 2-4 元件參數之萃取.....................................15 第三章 元件關鍵製程與開發................................27 3-1 電極與量子點之自我對準技術.........................27 3-2 Si3N4 or SiO2對Si有高選擇比之乾式蝕刻...............28 第四章 元件完整製作流程..................................41 4-1 鍺量子點的形成.....................................41 4-2 FinFET-like鍺量子點之單電子/電洞電晶體製作流程.......43 第五章 元件電特性分析與製程檢討..........................59 5-1 量測儀器與方法.....................................59 5-2 閘極調變下之電流曲線...............................59 5-3 量子點內部之電性結構...............................58 5-4 非對稱之ID-VDS電流特性.............................62 5-5 元件分析與製程檢討.................................64 第六章 總結與未來展望....................................75 參考文獻.................................................76
參考文獻	[1] 陳啟東， 「單電子電晶體簡介」， 物理雙月刊，第二十六卷，第三期， 2004年6月 [2] Lei Zhuang, Lingjie Guo, and Stephen Y.Chou, “Silicon single-electron quantum-dot transistor switch operating at room temperature”, Applied Physics Letters, Vol. 72, 9 March 1998 [3] Hiroki Lshikuro and Toshiro Hiramoto, “Quantum mechanical effect in silicon quantum dot in a single-electron transistor”, Applied Physics Letters, Vol. 71, 22 December 1997 [4] B. H. Choi and S. W. Hwang, “Fabrication and room-temperature characterization of a silicon self-assembled quantum-dot transistor”, Applied Physics Letters, Vol.73, 23 November 1998 [5] Masumi Saitoh, Hidehiro Harata and Toshiro Hiramoto, “Room-temperature Demonstration of Integrated Silicon Single-Electron Transistor Circuit for Current Switching and Analog Pattern Matching”, IEEE, 2004 [6] P. W. Li, W. M. Liao, David M. T. Kuo and S. W. Lin, “Fabrication of a Germanium quantum dot single-electron transistor with large Coulomb-blockade oscillations at room temperature”, Applied Physics Letters, Vol. 85, 30 August 2004 [7] P. W. Li, David M. T. Kuo, W. M. Liao and W. T. Lai, “Study of tunneling current through germanium quantum-dot single-hole and –electron transistors”, Applied Physics Letters, Vol. 88, 25 May 2006 [8] Donald A. Neamen, “Semiconductor Physics & Devices”, [9] J. Weis, R. J. Haug, K. v. Klitzing and K. Ploog, “Transport spectroscopy of a confined electron system under a gate tip”, Physical Review B, Vol. 46, 15 November 1992 [10] Digh Hisamoto, Member, IEEE, Wem-chin Lee, Jakub Kedzierski, Hideki Takeuchi, Kazuya Asano, Member, IEEE, Chalres Kuo, Erik Anderson, Tsu-Jae King, Jeffrey Bokor, Fellow, IEEE, and Chenming Hu, Fellow, IEEE, “FinFET – A Self-Aligned Double-Gate MOSFET Scalable to 20 nm”, IEEE TED, Vol. 47, December 2000 [11] 莊達人編著，「VLSI製造技術」，第八章 [12] 黃俊凱，楊忠諺，「微機電蝕刻氣體的選擇」，奈米通訊，第九卷，第三期 [13] L. Rolland, M. C. Peignon, Ch. Cardinaued, G. Turban, “SiO2/Si Selectivity in high density CHF3/CH4 plasma: role of the fluorocarbon layer”, Microelectronic Engineering, Vol. 53, 2000 [14] H. K. Liou, P. Mei, U. Gennser and E. S. Yang, “Effect of Ge concentration on SiGe oxidation behavior”, Applied Physics Letters, Vol. 59, 1991 [15] P. W. Li, W. M. Liao and S. W. Lin, “Formation of atomic-scale germanium quantum-dot by selective oxidation of SiGe/Si-on-insulator”, Applied Physics Letters, Vol. 83, 1 December 2003 [16] W. T. Lai and P. W. Li, “Growth kinetics and related physical/electrical properties of Ge quantum dot formed by thermal oxidation of Si1-xGex-on-insulator”, Nanotechnology, Vol. 18, 2007 [17] P. W. Li, David M. T. Kuo, W. M. Liao, and W. T. Lai, “Study of tunneling currents through germanium quantum-dot single-hole and –electron transistors”, Applied Physics Letters, Vol. 88, 2006.
指導教授	李佩雯(Pei-Wen Li)	審核日期	2007-7-11
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