適用於DVB-T/H系統之低功率混合基數單埠記憶體模式快速傅利葉轉換處理器設計

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林政亮(Jeng-liang Lin) 查詢紙本館藏

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論文名稱

適用於DVB-T/H系統之低功率混合基數單埠記憶體模式快速傅利葉轉換處理器設計
(Low Power Mixed-Radix Single-Port Memory-Based FFT Processors for DVB-T/H System Applications)

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摘要(中)

隨著無線通訊普遍的發展，正交分頻多工(OFDM)和分離複頻(DMT)這類的多載波調變技術更進一步的重視其研究。舉例來說，地面/手持式數位影像傳輸(DVB-T/H)、數位音訊傳輸(DAB)、非對稱式數位電話線(ADSL)、高速數位電話線(VDSL)、電力線橋接器(PLC)等…。在OFDM系統中，多載波調變技術是將其分解成多個子載波做平行處理。於是，快速傅利葉轉換(FFT)和逆向快速傅利葉轉換(IFFT)在OFDM系統中是重要且運算複雜的部分。所以，如何減少運算時功率的消耗和硬體面積便是我們所要考量的。
此篇論文提出一個低功率混合基數(LPMR)之快速傅利葉轉換處理器，其使用基數為4/2(radix-4/2)為理論基礎並且以單埠記憶體存取方式實現快速傅利葉之運算，藉此來達到低功率之功效。此外，改善記憶體存取方式可以降低ROM之切換頻度而且可以縮短其運算時間。LPMR快速傅利葉轉換處理器需要兩組單埠記憶體，其中每一組長度有N個位址，而且利用基數為4當作其基本運算單元，可以同時處理一組基數為4或是兩組基數為2之基本運算。以運算1024點LPMR快速傅利葉轉換處理器而言，需要1280個運算周期，但是其輸出率只需1216個運算周期，即可將資料輸出。LPMR快速傅利葉轉換處理器是採用TSMC 0.18μm 製程，並且適用於2/4/8K點快速傅利葉轉換之運算，利用工作站電路合成至50MHz。並在20MHz和45MNz測量其功率消耗，分別做8192點之快速傅利葉轉換，其個別可分為23.85mW和 54.2mW。此外，LPMR之合成面積為2,325,656μm2。由以上觀察，和其他文獻相比之中，LPMR快速傅利葉轉換處理器可以更進一步地降低功率消耗。

摘要(英)

As wireless communication popular development, multicarrier modulation techniques such as Orthogonal Frequency Division Multiplex (OFDM) and Discrete Multitone (DMT) have been placed importance on research further. For example, Digital Video Broadcasting-Terrestrial/Handheld (DVB-T/H), Digital Audio Broadcasting (DAB), Asymmetric Digital Subscriber Line (ADSL), Very-high-speed Digital Subscriber Line (VDSL), Powerline Communications (PLC), etc. Multicarrier modulation in OFDM system is realized by multi-subcarrier parallel operation. Consequently, Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) are the most part and complicated computation in OFDM system. So how to reduce the operation power and minimize the FFT hardware cost become more momentous.
The paper proposes a new Low Power Mixed-Radix (LPMR) Fast Fourier Transform (FFT) processor. It uses radix-4/2 algorithm and performs single-port memory to access data in order to reduce power consumption. In addition, the improved in-place strategy for the Mixed-Radix (MR) algorithm can decrease the number of times for ROM transition and make the latency shorten. The LPMR FFT processor requires only two N-words single-port memories. Its architecture only has one radix-4 butterfly unit which can perform one radix-4 butterfly or two radix-2 butterflies at one clock cycle. The computation cycles between the first to the last operation and the latency between the first input to the first output for 1024-point operation of LPMR FFT are 1280 and 1216 clock cycles, respectively. The LPMR FFT processor uses TSMC 0.18μm cell library for 2/4/8K-point operation and runs at 50MHz. The power consumption of the 8192-point LPMR FFT processor operating at 20MHz and 45MHz are 23.85mW and 54.2mW, respectively. Besides, the area of 2/4/8K-point LPMR FFT processor is 2,365,656μm2. Therefore, the architecture of the LPMR FFT processor can further reduce power consumption and area comparing to the existing FFT processors on literatures.

關鍵字(中)

★ 快速傅利葉轉換
★ 低功率快速傅利葉轉換

關鍵字(英)

★ low power fft
★ fft

論文目次

第一章前言………………………………………………………..........1
第二章 DVB-T 系統簡介...……………………..……......…….....2
2.1 分頻多工FDM 與正交分頻多工OFDM 之差異 ................................. 2
2.2 DVB-T 系統與規格 ................................................................................ 3
第三章快速傅利葉轉換(FFT)理論……................................................6
3.1 基數為2 之快速傅利葉轉換(Radix-2 FFT)理論 .................................. 6
3.1.1 離散時間快速傅利葉轉換(DFT)理論 ................................................... 6
3.1.2 從頻域角度拆解基數為2 之離散快速傅利葉轉換(DIF) .................... 7
3.1.3 從時域角度拆解基數為2 之離散快速傅利葉轉換(DIT) .................... 9
3.2 基數為4 之快速傅利葉轉換(Radix-4 FFT)理論 ................................ 10
3.3 基數為22 之快速傅利葉轉換(Radix-22 FFT)理論 .............................. 13
3.4 基數為8 之快速傅利葉轉換(Radix-8 FFT)理論 ................................ 14
3.5 基數為23 之快速傅利葉轉換(Radix-23 FFT)理論………..………….17
3.6 基數為16、基數為32 快速傅利葉轉換(Radix-16、Radix-32 FFT)理論.18
3.7 分裂基數2/4、分裂基數2/8 快速傅利葉轉換(Split-Radix 2/4、Split-Radix 2/8 FFT)理論.18
第四章管線式和記憶體式架構之快速傅利葉轉換……..……...…..21
4.1 單一回授路徑(SDF)快速傅利葉轉換架構設計 ................................. 21
4.1.1 基數為2 之SDF 架構運算 .................................................................. 21
4.1.2 基數為4 之SDF 架構運算 .................................................................. 22
4.1.3 基數為22 之SDF 架構運算 ................................................................. 23
4.1.4 基數為8 之SDF 架構運算 .................................................................. 24
4.1.5 基數為23 之SDF 架構運算 ................................................................. 25
4.1.6 SDF 架構各式FFT 運算總結……..…………………………...……..25
4.2 多重路徑交換器(MDC)快速傅利葉轉換架構設計……...…………..27
4.2.1 基數為2 之MDC 架構運算……………………………...…………..27
4.2.2 基數為4 之MDC 架構運算……………………………...…………..28
4.2.3 基數為22 之MDC 架構運算……………………………...………… 29
4.2.4 基數為8 之MDC 架構運算……………………………...…………..29
4.2.5 基數為23 之MDC 架構運算……………………………...…………..30
4.2.5 MDC 架構各式FFT 運算總結….……………………………...……..30
4.3 記憶體式快速傅利葉轉換架構設計………..…………….…………..32
4.3.1 TSMC CL018G製程技術….…………..……....……………….……..32
4.3.1.a 高速雙埠同步SRAM(RA2SH)...........................................…….……..32
4.3.1.b 高速雙埠同步Register File(RF2SH).…………………………..……..33
4.3.1.c 高速單埠同步SRAM(RA1SH)...………………………………….…..33
4.3.1.d 高速單埠同步Register File(RF1SH)…………………………….……34
4.3.2 各種記憶體式快速傅利葉架構設計…………………………………35
4.3.2.a 適用於DMT/OFDM 應用之記憶體式快速傅利葉轉換處理器[9]…..35
4.3.2.b 適用於VDSL 收發機之記憶體式快速傅利葉轉換處理器[10]………..37
4.3.2.c 高效能架構之記憶體式快速傅利葉轉換[11]………………………..…...38
4.3.2.d 使用新穎存取策略之連續流動混合基數快速傅利葉轉換處理器[12]…...39
4.3.3 記憶體式架構各式FFT 運算總結..…………………………………43
第五章單埠記憶體式順序輸出(LSOM)快速傅利葉轉換處理器……...…….44
5.1 LSOM 快速傅利葉轉換處理器架構 ................................................... 44
5.2 LSOM 控制電路 ................................................................................... 48
5.2.1 LSOM 之記憶體控制電路 ................................................................... 48
5.2.2 LSOM 之組合邏輯元件控制電路 ....................................................... 52
5.2.3 LSOM 之ROM 控制電路 .................................................................... 54
5.3 記憶體式FFT 運算電路分析與比較 ................................................... 55
第六章適用於DVB-T/H 系統之低功率混合基數(LPMR)單埠記憶體式快速傅
利葉轉換處理器…………………………………………..…….....…58
6.1 LPMR快速傅利葉轉換處理器架構….…………………………..…..58
6.2 LPMR控制電路…………………….……………………………..…..63
6.2.1 LPMR 之記憶體控制電路.………....……………………………..…..63
6.2.2 LPMR 之組合邏輯元件控制電路……...…..……………………..…..67
6.3 管線式和記憶體式之FFT 運算架構比較.………………………..…..70
6.4 LPMR 之DVB-T/H 系統應用…….......…..……………………..…..73
第七章硬體實作與模擬結果..................................................................76
7.1 浮點模擬與定點運算……….….........…..……………………..…..76
7.2 FPGA 之模擬結果…….……….…........…..……………………..…..78
7.3 PrimePower 模擬LPMR之功率….…......…..……………………..…..80
第八章結論與展望...................................................................84
參考文獻……….……………………………………………………….86

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指導教授

薛木添(Muh-tian Shiue)

審核日期

2008-1-2

推文