博碩士論文 945401012 詳細資訊




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姓名 龔存雄(Cihun-Siyong Gong)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 用於植入式生醫電子微系統之高效能積體電路的設計與實現
(On the Design and Implementation of Efficient Integrated Circuits for Bioimplantable Electronic Microsystems)
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摘要(中) 由於近十年來積體電路技術的快速發展,使得將有著大量電晶體數量的複雜訊號處理系統實現於單一晶片上變為可能,同時也開啟了重建人類失去的複雜感官之契機。 現今,諸如像耳蝸植入物此類的植入式晶片,已能用於重新取得絕大部份已失去的聽覺感官。 對視盲患者而言,視覺輔具已被視為是一種極具潛力的治癒方式。 然而,雖然此類輔具已於過去數十年間被廣泛研究,於實際應用前仍有許多尚待克服之瓶頸。 本論文旨在實現一可應用於視覺輔具之高效能系統。 然而雖然本文中所提出的設計主要係針對視覺輔具之應用,這些被提出的技術亦能輕易地被用於其它的輔具系統,而僅需少量的修改。
就論文的內容部份,吾人首先提出一應用於無線供電式系統之高效能鍵控移幅解調變器,其克服了諸多前人所提出架構之限制。 藉由一自取樣的概念,此調變器能同時兼具可操作於低調變索引與無電容電阻之優點。 經由實際透過0.18 微米金氧半製程進行實現,所提出的解調器僅具有32.3×14.5 um^2。 模擬與量測結果顯示所提出的解調器於電路本身特性上可於2 MHz 的載波情況下完成高達50%調變率的解調,功耗約為336 uW。 此外,結果亦顯示所提出的解調器可在低於5.5%的調變指標下正確解調。
接著,吾人提出一植基於絕熱切換之全積體化具能量感知之無線供電輔具系統架構。 所提出的架構當操作在2 MHz 的載波時其內建之模式I 可允許240 個刺激通道每秒執行240 次掃描(240 張影格),而在模式II 時的影格量更可達到模式I 可允許量的三倍之多,因而適合諸如視覺輔具這般須即時掃描的多通道輔具。 為能迎合在感知方面更高的空間解析度,此雛型系統已以16 通道為基礎之刺激概念進行設計進而使其能被拓展至各種不同的實驗需求。 經由透過0.18 微米製程進行實現,所提出的輔具系統相較於傳統設計架構可有效降低高達80%的解調誤碼率,並可同時節省約18%的外部發送平台電流消耗量。 然而本系統雖具有改善傳統(非使用能量回復式技術)架構之解調誤碼率與能量效益之優點,卻也造成其本身除解調器外的其它部份位元錯誤率升高之缺陷。 此誤碼率之上升主要係與所採用的能量回復技術於邏輯求值時所具有的死區有關。
針對此缺陷,吾人於文中第三個主要部份提出一新式不可逆能量回復式邏輯。 此新式能量回復邏輯承接了半靜態能量回復邏輯家族之優點,卻有著改善的驅動能力與電路強健度。 相較於半靜態能量回復邏輯,此新式能量回復式邏輯於相同操作條件下具有無"保持"相位之特色,因而毋需半靜態能量回復邏輯家族所須之回授保持電路。 這樣的特色使其在整體面積與功耗上均獲得顯著提升。 此外,當以相同的功率時脈頻率進行測試時,所提出之新式不可逆能量回復式邏輯的運作(吞吐)量可達半靜態能量回復邏輯之兩倍。 吾人亦於文中對所提出之邏輯類型與其他可達相似效能之邏輯類型(次臨限邏輯)進行比較。 為證實此新式邏輯之可使用性,一個以所提出的邏輯類型所設計之八位元移位暫存器已使用0.18 微米製程進行實現。 模擬與量測結果均證實所提出邏輯之功能與其優越性,意昧著所提出的邏輯可用於實現高效能具能量感知之超大型積體電路系統以及去改善吾人所提出的輔具系統之缺陷。
在文中的最後部份,吾人論及兩個可用於更進一部提升系統效能之技術。 在此部份首先談到的為一以低功耗、低成本,與真正低複雜度實現為特色之新式鍵控移相解調器。 藉著結合資料之無線供電式傳輸所具有之高訊雜比之優勢,本架構可在不需要複雜須鎖相迴路之載波回復電路之情況下完成鍵控移相訊號之解調。 經由以0.18 微米製程進行設計實現,所提出的鍵控移相解調器可在以真實無線聯結平臺進行測試的情況下完成800 Kbps 的數據解調,而僅耗費低於59 uW。 此部份第二個主軸便是提出一全積體化低損耗金氧半整流器。 藉由使用達成幾乎理想切換之高效能主動二極體,當以0.18微米製程完成設計製造並以真實的無線聯結平臺進行驗證,所提出的架構可在不需任何特殊元件製程的情況下,達成超過90%的最大轉換效能。 與所提出之輔具系統相關的設計考量以及系統中所須用到的每個核心技術都將於本文中詳細闡述。
摘要(英) Thanks to the rapid advance in the technologies of integrated circuit (IC) during the last ten years, it is possible to realize a complex signal process system with large number of transistors in a single microchip, which creates the possibility of reconstructing lost sophisticated human sensations. Today, implantable chips, such as the cochlear implant, have been able to be used to regain the greater part of the sense of lost hearing. Visual prostheses have been considered potential cure for people who suffer from blindness. Though such prostheses have been extensively studied over the decade, there are, however, still many bottlenecks that need to be overcome prior to actual application. This dissertation aims for accomplishing an efficient system for visual prostheses. While the designs presented in the dissertation are mainly for such applications, they are easy to be applied to other similar systems with different prosthetic purposes, with only minor modification of the system.
With regard to the contents of the dissertation, first of all, an ASK demodulator architecture capable of dealing with most of the previous limitations in an ASK-utilized medical implant, especially in want of being powered through wireless delivering, is proposed. It features the abilities of working on a very small modulation index and being provided without any R/C component(s) inside by means of a self-sampling scheme. Implemented in a 0.18-μm CMOS process, the demodulator occupies a die size of merely 32.3×14.5 (um×um). Analytic results from both simulation gradation and measurement phase show that the proposed circuit can operate at carrier frequency of 2 MHz and achieve a modulation rate of up to 50% when tested under an experimental set-up using signal generator. The average power consumption is in the vicinity of 336 uW. The results also indicate that the presented work can still perform a proper demodulation even with a modulation index is beneath 5.5%.
Second, a fully integrated energy-aware wirelessly powered prosthetic system architecture based on adiabatic switching has been developed. The proposed architecture can allow up to 40 frame/sec with 240 stimulus channels in mode I and three times the resolution at the same frame rate in mode II under a carrier frequency of 2 MHz, suitable for the multi-channel prostheses requiring real-time scanning such as visual prostheses. To cater to higher spatial resolution in sensation, the prototypical system has been constructed with a 16-channel-based stimulation scheme so that the design can be extended toward various experimental requirements. Fabricated in a
0.18-um CMOS process, the proposed prosthetic system has an 80% reduction in BER of the demodulated data and 18% saving in the average current consumption of the extraocular platform as compared with those designed in the conventional (non-energy-recovery) baseband architecture, showing the potential of the proposed system in improving overall system efficiency in spite of the weakness of the considerably increased fail-bit rate in other parts of itself. The increased fail-bit rate is mainly associated with the intrinsic dead zone in the logic evaluation in the employed energy recovery technique.
In response to the weakness, the design and experimental evaluation of a new type of irreversible energy recovery logic (ERL) families were conducted and are presented in the third part of the dissertation. The newly developed ERL inherits the advantages of quasi-static ERL (QSERL) family, but is with improved driving ability and circuit robustness. It also features no hold phase compared to its QSERL counterpart under the same operation conditions; thereupon no feedback keeper is required. This yields considerable improvements in area and power overheads as a whole. Moreover, the throughput of the newly developed energy recovery logic becomes twice as high as that of QSERL when tested with the same frequencies of power clocks. Comparison between the proposed logic style and other known logic style achieving iso-performance, namely, subthreshold logic is given. To demonstrate the workability of the proposed logic style, an 8-bit shift register, designed in the proposed logic style, has been fabricated in the 0.18-um CMOS process. Both simulation and measurement results verify the functionality and advantages of the proposed logic, suggesting that it is suitable for implementing performance-efficient and energy-aware very-large-scale integration (VLSI) circuitry and being used in the energy-aware electronic prosthetic system to cope with the choke point mentioned above namely the increased fail-bit rate.
In the last part of the dissertation, two techniques are presented to further enhance the system efficiency. The first is an efficient phase-shift keying demodulator (PSKD) featuring low power, low cost, and truly low-complexity implementation. By taking advantages of a high signal-to-noise ratio on wirelessly power-combined data transmission, the demodulation of the BPSK signal can be performed without the complex carrier recovery circuits requiring phase-locked loop (PLL). The proposed PSK demodulator, the circuit schematic of which has been fabricated in the 0.18-um CMOS process, recovers a binary data rate with up to 800 Kbps while consumes power less than 59 uW when tested in a real wireless-link setup. The second refers to a fully integrated low-loss CMOS rectifier. By making use of high-performance active diodes fulfilling almost ideal switching (zero forward voltage drop) and circuit to be provided with negative resistance, the proposed design is able to achieve a maximum of more than 90% conversion efficiency when fabricated in the 0.18-um standard CMOS process and tested in a real wireless link, without any special device requiring additional manufacturing procedures. The design considerations along with the proposed system and each of the key building block techniques will be detailed in the dissertation.
關鍵字(中) ★ 輔具
★ 生醫
★ 電路與系統
★ 混合訊號
★ 可植入式
關鍵字(英) ★ prosthesis
★ medical
★ circuits and systems
★ mixed-signal
★ implantable
論文目次 Abstract iv
List of Tables xiii
List of Figures xiv
Chapter 1 Introduction 1
1.1 Overview of Electronic Implant System. . . . . . 2
1.1.1 Transmission Type. . . . . . 2
1.1.2 Implant Functionality. . . . . . 3
1.2 Motivation. . . . . . 4
1.3 Design Considerations. . . . . . 5
1.4 Organization of the Dissertation. . . . . . 7
Chapter 2 RC-Free ASK Demodulator for Implantable Systems 9
2.1 Chapter Overview. . . . . . 9
2.2 Overview of ASKD Families. . . . . . 10
2.3 System Considerations and Circuit Design. . . . . . 18
2.3.1 ASKDs in Subminiature Wireless-Powering Devices. . . . . . 18
2.3.2 Circuit Topology. . . . . . 24
2.3.3 Simulation Analysis. . . . . . 31
2.4 Results and Discussion . . . . . . 35
2.5 Summary of the Chapter. . . . . . 41
Chapter 3 Implantable Circuitry with Adiabatic Switching Technique 43
3.1 Chapter Overview. . . . . . 43
3.2 Architecture. . . . . . 43
3.3 System Implementation. . . . . . 47
3.3.1 Building Block Technique. . . . . . 47
3.3.2 Adiabatic Principle. . . . . . 48
3.3.3 Irreversible Energy Recovery Logic Families. . . . . . 49
3.3.4 ADL-related family. . . . . . 50
3.3.5 2N2P-related family. . . . . . 50
3.3.6 PAL-related family. . . . . . 52
3.3.7 TSEL-related family. . . . . . 52
Chapter 4 Circuit Design for Adiabatic Electronic Prosthesis 60
4.1 Chapter Overview. . . . . . 60
4.2 Regulator, Voltage Reference Circuit, and Demodulator. . . . . . 60
4.3 Power Clock Generator. . . . . . 62
4.4 Clock Regeneration Circuit and Check Decision Circuit. . . . . . 63
4.5 Power-On-Reset Circuit, Data Recovery Circuit, and Frame Generator 64
4.6 Serial-to-Parallel Converter, Decoder, and Image Buffer. . . . . . 65
4.7 Programmable Controller. . . . . . 66
4.8 Microstimulator. . . . . . 66
4.9 Results. . . . . . 69
4.10 Summary of Chapter 3 and Chapter 4. . . . . . 72
Chapter 5 Design Improvement - Complementary Energy Path Adiabatic Logic 83
5.1 Chapter Overview. . . . . . 83
5.2 Limitations in Irreversible ERL Families. . . . . . 85
5.3 Complementary Energy Path Adiabatic Logic. . . . . . 86
5.3.1 Operation and Analysis of CEPAL. . . . . . 86
5.3.2 Leakage Impact. . . . . . 88
5.3.3 Fault Tolerance. . . . . . 89
5.3.4 Driving Ability. . . . . . 89
5.3.5 Implementation Cost and Power Efficiency. . . . . .90
5.3.6 Vt Mismatch. . . . . . 91
Chapter 6 CEPAL versus Subthreshold Logic 99
6.1 Chapter Overview. . . . . . 99
6.2 Choice of Subthreshold Logic. . . . . . 100
6.3 Comparison. . . . . . 102
6.4 Results and Analysis. . . . . . 106
6.5 Summary of Chapter 5 and Chapter 6. . . . . . 110
Chapter 7 Further Optimization - Quasi-Coherent PSK Demodulator 115
7.1 Chapter Overview. . . . . . 115
7.2 Carrier Recovery and PSK Demodulation. . . . . . 117
7.3 Quasi-Coherent PSK Demodulator. . . . . . 118
7.4 Results. . . . . . 124
7.5 Summary of the Chapter. . . . . . 124
Chapter 8 Further Optimization - Fully Integrated CMOS Rectifier 126
8.1 Chapter Overview. . . . . . 126
8.2 Prior Arts and Proposed Design. . . . . . 128
8.3 Results. . . . . . 133
8.4 Summary of the Chapter. . . . . . 136
Chapter 9 Conclusions and Future Works 138
9.1 Conclusions. . . . . . 138
9.2 Future Works. . . . . . 139
Bibliography 142
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指導教授 薛木添(Muh-Tian Shiue) 審核日期 2008-11-12
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