低功率與可自我修復之三元內容定址記憶體設計

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：12

、訪客IP：3.21.93.44

姓名

賴駿凱(Chun-Kai Lai) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

低功率與可自我修復之三元內容定址記憶體設計
(Design of a Low-Power and Self-Repairable Ternary Content Addressable Memory)

相關論文

★ 應用於三元內容定址記憶體之低功率設計與測試技術	★ 用於隨機存取記憶體的接線驗證演算法
★ 用於降低系統晶片內測試資料之基礎矽智產	★ 內容定址記憶體之鄰近區域樣型敏感瑕疵測試演算法
★ 內嵌式記憶體中位址及資料匯流排之串音瑕疵測試	★ 用於系統晶片中單埠與多埠記憶體之自我修復技術
★ 用於修復嵌入式記憶體之基礎矽智產	★ 自我修復記憶體之備份分析評估與驗證平台
★ 使用雙倍疊乘累加命中線之低功率三元內容定址記憶體設計	★ 可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計
★ 多核心系統晶片之診斷方法	★ 應用於網路晶片上隨機存取記憶體測試及修復之基礎矽智產
★ 應用於貪睡靜態記憶體之有效診斷與修復技術	★ 應用於內嵌式記憶體之高效率診斷性資料壓縮與可測性方案
★ 應用於隨機存取記憶體之有效良率及可靠度提升技術	★ 應用於特殊半導體記憶體之測試與可靠性設計技術

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

三元內容定址記憶體(TCAM)在數位系統中被廣泛的使用，尤其是網路應用。可提供平行比對的功能，不過，TCAM擁有複雜的功能。此複雜的功能導致TCAM變成一個面積消耗及功率消耗的元件。因此，面積小及低功率是兩項重要的挑戰在設計一個具有成本效益的TCAM中。並且，良率改善的技術是非常重要對於TCAM而言，因為TCAM的面積通常是非常大的。
本篇論文，我們提出一個低功率TCAM使用混合樹狀NAND/NOR命中線(Hybrid Tree-NAND/NOR match line)。混合樹狀NAND/NOR的架構可以增加NAND部分的位元數目在一排TCAM中，此排造成的比較功率及比較延遲可藉由NAND部份的數目增加而減少到最低限度。因此，提出TCAM使用混合樹狀NAND/NOR命中線的比較操作的能量是非常低。我們已實現一個32x64位元的TCAM使用混合樹狀NAND/NOR命中線。此測試晶片的測量結果顯示TCAM的功率消耗只有0.4122mW在110MHz。並且，能量消耗是非常低的，只有約1.90fJ/bit/search。相比之下，與現有在一般應用中的TCAMs，被提出來的TCAM能達到較佳的能量消耗。
我們還提出一個內建自我修復(BISR)電路關於TCAM的。在BISR電路中，一個可編程序的內建自我測試(BIST)電路被提出來測量TCAM的功能缺陷和一種新的重置機制被提出來對調缺陷的元件。不同於被廣泛使用的轉換多餘(shift redundancy)電路，提出的多餘重置電路帶來固定的延遲損失不管實現多餘電路的數目。實驗結果顯示BISR電路的延遲和面積成本分別都只大約0.85ns和21920um^2。

摘要(英)

Ternary content addressable memory (TCAM) is widely used in digital systems, especially for network applications. To support parallel comparison function, however, a TCAM has complex function. The complex function causes that the TCAM becomes an area-consuming and power-consumption component. Therefore, low-area and low-power are two major challenges in designing a cost-efficient TCAM. Also, yield improvement techniques are very important for the TCAM since the area of TCAM is usually very large.
In this thesis, we propose a low-power TCAM with hybrid tree-NAND/NOR match line. The hybrid tree-NAND/NOR structure can increase the number of bits of NAND-type cells in a TCAM word such that the compare power of the word and the compare delay caused by the NAND-type cells can be minimized. Therefore, the energy of compare operation of the proposed TCAM with hybrid NAND/NOR match lines is very low. We have implemented a 32x64-bit TCAM with hybrid NAND/NOR match lines. Measurement results of the TCAM test chip show that the power consumption of the TCAM is only about 0.4122mW at 110MHz. Also, the energy consumption is very low, which is only about 1.90fJ/bit/search. In comparison with the existing TCAMs for general applications, the proposed TCAM achieve better energy consumption.
We also propose a built-in self-repair (BISR) scheme for the TCAM. In the BISR scheme, a programmable built-in self-test circuit is proposed to test the functional faults of the TCAM and a novel reconfiguration mechanism is proposed to swap defective elements. Differing from the widely-used shift redundancy scheme, the proposed redundancy reconfiguration scheme incurs constant delay penalty regardless of the number of implemented redundancies. Experimental results show that the delay and the area cost of the BISR circuit are only about 0.85ns and 21920um^2, respectively.

關鍵字(中)

★ 三元內容定址記憶體
★ 備份電路
★ 低功率
★ 自我修復

關鍵字(英)

★ TCAM
★ Low Power
★ Redundancy
★ BISR

論文目次

Chapter 1 Introduction....................................1
Chapter 2 Overview of Content Addressable Memories........6
2.1 Typical CAM Architecture..............................6
2.2 CAM Word Structures...................................8
2.3 CAM Cell Structures...................................9
Chapter 3 Design of Hybrid Tree-NAND/NOR Match Lines.....12
3.1 Proposed Hybrid Tree-NAND/NOR Match Lines............12
3.1.1 Design of Tree-NAND and NOR Segments...............15
3.1.2 Analysis and Comparison Results....................23
3.2 Design of Shift Redundancy...........................28
3.2.1 Row Redundancy.....................................29
3.2.2 Column Redundancy..................................30
Chapter 4 A Built-In Self-Repair Technique for CAMs......32
4.1 Architecture of Built-In Self-Repair.................34
4.2 Design a Programmable Built-In Self-Test.............43
4.3 Simulation Results of Built-In Self-Repair...........47
Chapter 5 Experimental Results and Test Chip Measurement Results..................................................55
5.1 Pre-layout Simulation................................55
5.1.1 TCAM Array Simulation..............................55
5.1.2 Peripheral Circuit Simulation......................60
5.2 Physical Layout of TCAM Cells........................62
5.3 Post-layout Simulation...............................63
5.4 Test Chip Measurement Results........................66
Chapter 6 Conclusions and Future Work....................77
Reference................................................79

參考文獻

[1] K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE J. Solid State Circuits (JSSC), vol. 41, no. 3, pp. 712-727, March 2006.
[2] C. A. Zukowski and S.-Y. Wang, “Use of selective precharge for low power content-addressable memories,” in Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS), 1997, vol. 3, pp. 1788-1791.
[3] T. Juan, T. Lang, and J. J. Navarro, “Reducing TLB power requirements,” in Int. Symp. on Low Power Electronics and Design, Monterey, Aug. 1997, pp. 196-201.
[4] K.-J. Lin and C.-W. Wu, “A low-power CAM design for LZ data compression,” IEEE Trans. Computers, vol. 49, no. 10, pp. 1139-1145, Oct. 2000.
[5] G. Thirugnanam, N. Vijaykrishnan, and M. J. Irwin, “A novel low power CAM design,” in Proc. 14th IEEE ASIC/SOC Conf., Arlington, Sept. 2001, pp. 198-202.
[6] Y.-L. Hsiao, D.-H. Wang, and C.-W. Jen, “Power modeling and low-power design of content addressable memories,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Sydney, May 2001, pp. 926-929.
[7] H. Miyatake, M. Tanaka, and Y. Mori, “A design for high-speed low-power CMOS fully parallel content-addressable memory macros,” IEEE J. Solid-State Circuits (JSSC), vol. 36, no. 6, pp. 956-968, Jun. 2001.
[8] C.-S. Lin, J.-C. Chang, and B.-D. Liu, “A low-power precomputation-based fully parallel content-addressable memory,” IEEE J. Solid State Circuits (JSSC), vol. 38, no. 4, pp. 654-662, Apr. 2003.
[9] I. Arsovski and A. Sheikholeslami, “A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories,” IEEE J. Solid State Circuits (JSSC), vol. 38, no. 11, pp. 1958-1966, Nov. 2003.
[10] K. Pagiamtzis and A. Sheikholeslami, “A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme,” IEEE J. Solid-State Circuits (JSSC), vol. 39, no. 9, pp. 1512-1519, Sept. 2004.
[11] Efthymiou and J. D. Garside, “A CAM with mixed serial-parallel comparison for use in low energy caches,” IEEE Trans. VLSI Systems, vol. 12, no. 3, pp. 325-329, March 2004.
[12] B.-D. Yang and L.-S. Kim, “A low-power CAM using pulsed NAND–NOR match-line and charge-recycling search-line driver,” IEEE J. Solid State Circuits (JSSC), vol. 40, no. 8, pp. 1736-1744, Aug. 2005.
[13] H.-Y. Li, C.-C. Chen, J.-S. Wang, and C. Yeh, “An AND-type match-line scheme for high-performance energy-efficient content addressable memories,” IEEE J. Solid State Circuits (JSSC), vol. 41, no. 5, pp. 1108-1119, May 2006.
[14] Y.-J. Chang, Y.-H. Liao, and S.-J. Ruan, “Improve CAM power efficiency using decoupled match line scheme,” in Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), Apr. 2007, pp. 1-6.
[15] Y.-J. Chang, “Two-layer hierarchical matching method for energy-efficient CAM design,” IEE Electronics Letters, vol. 43, no. 2, Jan. 2007, pp. 80-82.
[16] I. Arsovski, T. Chandler, and A. Sheikholeslami, “A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme,” IEEE J. Solid-State Circuits (JSSC), vol. 38, no.1, pp. 155-158, Jan. 2003.
[17] H. Noda, K. Inoue, M. Kuroiwa, A. Amo, A. Hachisuka, H. J. Mattausch, T. Koide, S. Soeda, K. Dosaka, and K. Arimoto, “A 143MHz 1.1W 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture,” in Digest of IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2004, pp. 208-210.
[18] H. Noda, K. Inoue, M. Kuroiwa, F. Igaue, K. Yamamoto, H. J. Mattausch, T. Koide, A. Amo, A. Hachisuka, S. Soeda, I. Hayashi, F. Morishita, K. Dosaka, K. Arimoto, K. Fujishima, K. Anami, and T. Yoshihara, “A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture,” IEEE J. Solid State Circuits (JSSC), vol. 40, no. 1, pp. 245-253, Jan. 2005.
[19] S. Choi, K. Sohn, and H.-J. Yoo, “A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture,” IEEE J. Solid-State Circuits (JSSC), vol. 40, no. 1, pp. 254-260, Jan. 2005.
[20] V. Ravikumar, R. N. Mahapatra, and L. N. Bhuyan, “EaseCAM: an energy and storage efficient TCAM-based router architecture for IP lookup,” IEEE Trans. Computers, vol. 54, no. 5, pp. 521-533, May 2005.
[21] W. Wu, J. Shi, L. Zuo, and B. Shi, “Power-efficient TCAMs for bursty access patterns,” IEEE Micro, vol. 25, no. 4, pp. 64-72, Aug. 2005.
[22] M.-J. Akhbarizadeh, M. Nourani, and C.D. Cantrell, “Prefix segregation scheme for a TCAM-based IP forwarding engine,” IEEE Micro, vol. 25, no. 4, pp. 48-63, Aug. 2005.
[23] G. Kasai, Y. Takarabe, K. Furumi, and M.Yoneda, “200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), 2003, pp. 387-390.
[24] D. S. Vijayasarathi, M. Nourani, M. J. Akhbarizadeh, and P. T. Balsara, “Ripple-precharge TCAM: a low-power solution for network search engines,” in Proc. IEEE International Conference on Computer Design (ICCD), Oct. 2005, pp. 243-248.
[25] J.-S. Wang, C.-C. Wang, and C. Yeh, “TCAM for IP-address lookup using tree-style AND-type match lines and segmented search lines,” in Digest of IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2006, pp. 577-586.
[26] S.-W. Chang, P.-T. Huang, and W. Hwang, “A novel butterfly match-line scheme with don't-care based hierarchical search-line for TCAM”, in Proc. 17th VLSI/CAD Symposium, Aug. 2006, pp. 286-289.
[27] P.-T. Huang, S.-W. Chang, W.-Y. Liu, and W. Hwang, “A 256x128 energy-efficient TCAM with novel low power schemes,” in Proc. IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2007, pp. 1-4.
[28] K. R. Viveka, A. Kawle, and B. Amrutur, “Low power pipelined TCAM employing mismatch dependent power allocation technique,” in Proc. IEEE International Conference on VLSI Design (VLSID), Jan. 2007, pp. 638-646.
[29] N. Mohan and M. Sachdev, “Low-capacitance and charge-shared match lines for low-energy high-performance TCAMs,” IEEE J. Solid State Circuits (JSSC), vol. 42, no. 9, pp. 2054-2060, Sept. 2007.
[30] N. Mohan and M. Sachdev, “A static power reduction technique for ternary content addressable memories,” in Proc. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), vol. 2, May 2004, pp. 711-714.
[31] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair design for RAMs with 2-D redundancies,” IEEE Trans. Very Large Scale Integration Systems, vol. 13, no. 6, pp. 742-745, Jun. 2005.
[32] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, “A simulator for evaluating redundancy analysis algorithms of repairable embedded memories,” in IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), July. 2002, pp. 68-73.
[33] R. Nadkarni, I. Arsovski, R. Wistort, and V. Chickanosky, “Improved match-line test and repair methodology including power-supply noise testing for content-addressable memories,” in Proc. IEEE Int. Test Conf. (ITC), Oct. 2006, pp. 1-9.
[34] H. Noda, K. Inoue, H. J. Mattausch, T. Koide, K. Dosaka, K. Arimoto, K. Fujishima, K. Anami, and T. Yoshihara, “Embedded low-power dynamic TCAM architecture with transparently scheduled refresh,” IEICE Trans. on Electronics, vol. E88-C, no. 4, pp. 622-629, Apr. 2005.
[35] C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, “A built-in self-test and self-diagnosis scheme for embedded SRAM,” in Proc. IEEE Asian Test Symp. (ATS), Dec. 2000, pp. 45-50.
[36] J.-F. Li, “Testing ternary content addressable memories with comparison faults using march-like tests,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 5, May 2007, pp. 919-931.
[37] F. Shafai, K. J. Schultz, G. F. R. Gibson, A. G. Bluschke, and D. E. Somppi, “Fully parallel 30-MHz, 2.5-Mb CAM,” IEEE J. Solid-State Circuits (JSSC), vol. 33, no. 11, pp. 1690-1696, Nov. 1998.
[38] C.-C. Chen, H.-Y. L, and J.-S. Wang, “The split-path AND-type match-line scheme for very high-speed content addressable memories,” Asian Solid-State Circuits Conference, Nov. 2005, pp. 525-528.
[39] A. Roth, D. Foss, R. McKenzie, and D. Perry, “Advanced ternary CAM circuits on 0.13um logic process technology,” in Proc. IEEE Custom Integrated Circuits Conference, Oct. 2004, pp. 465-468.
[40] X. Yang, S. Sezer, J. McCanny, and D. Burns, “Novel Content Addressable Memory Architecture for Adaptive Systems,” IEEE Second NASA/ESA conference on Adaptive Hardware and Systems (AHS), Aug. 2007, pp. 633-640.
[41] J.-F. Li, J.-C. Yeh, R.-F. Huang, C.-W. Wu, P.-Y. Tsai, A. Hsu, and E. Chow, “A built-in self-repair scheme for semiconductor memories with 2-D redundancies,” in Proc. IEEE Int. Test Conf. (ITC), Sept. 2003, pp. 393-402.
[42] T.-W. Tseng, J.-F. Li, C.-C. Hsu, A. Pao, K. Chiu, and E. Chen, “A reconfigurable built-in self-repair scheme for multiple self-repairable RAMs in SOCs,” in Proc. IEEE Int. Test Conf. (ITC), Oct. 2006, pp. 1-8.
[43] Y.-J. Huang, D.-M. Chang, and J.-F. Li, “A built-in redundancy-analysis scheme for self-repairable RAMs with two-level redundancy,” in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Oct. 2006, pp. 362-370.
[44] J.-F. Li and C.-H. Wu, “Verification methodology for built-in self-repairable memory systems,” in Proc. IEEE Asian Test Symp. (ATS), Nov. 2006, pp. 109-114.
[45] T.-W. Tseng, C.-H. Wu, Y.-J. Huang, J.-F. Li, Alex Pao, K. Chiu, and E. Chen, “A built-in self-repair scheme for multiport RAMs,” in Proc. IEEE VLSI Test Symp. (VTS), May 2007, pp. 355-360.
[46] J.-F. Li, S.-K. Lu, S.-A. Hwang, and C.-W. Wu, “Easily testable and fault-tolerant FFT butterfly networks,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 9, pp. 919-929, Sep. 2000.
[47] S. K. Lu, “A novel built-in self-repair approach for embedded RAMs,” Journal of Electronic Testing: Theory and Application, vol. 19, pp. 315-324, June 2003.
[48] J.-S. Wang and C.-H. Huang, “High-speed and low-power CMOS priority encoders,” IEEE J. Solid-State Circuits (JSSC), vol. 35, no. 10, pp. 1511-1514, Oct. 2000.

指導教授

李進福(Jin-Fu Li)

審核日期

2008-4-29

推文