||Thanks to the rapid progress of semiconductor technology for the past 30 several years, many high-tech products could be hence developed. Therefore, we could hereby understand how important the role that semiconductor plays in the industrial development. However, semi- conductor is a field with high thresholds in technology, cost and standardization, therefore, all semiconductor companies aim for increasing their profitability without any exception. Among so many methodologies, Yield Management is highly emphasized and researched. In brief, Yield could be defined as a percentage of good chips over all chips in production line. In order to gain Yield enhancement and increase the profitability, we must predict Yield by analyzing the huge amount of data generated during the manufacturing process systematically.|
In this thesis, several popular Yield Models in semiconductor field were evaluated by the same Defect Inspection data to understand which one is the best for each Defect Inspection Step, including those Yield Models developed by the Case Company. The Case Company intended to develop the simple Yield Models based on the classifications of the tested chips, and tried to apply such Models on all Defect Inspection Steps. After evaluation, this thesis could contribute several decision rules to the management level of the Case Company to help make decisions.
According to the above evaluation, we found those Yield Models developed by the Case Company all have pretty good performance in Yield prediction. There were about 58% of the Defect Inspection Steps revealed that the Yield Models developed by the Case Company had both precise and stable results in prediction. The prediction results became even better, 100%, if we only considered precision to evaluate those Yield Models.
1. Mirza, A. I., Donoghue, G.O., Drake, A.W. and Graves, S.C., 1995, “Spatial Yield Modeling for Semiconductor Wafers”, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, p. 276-281.
2. Murphy, B.T., 1964, “Cost-Size Optima of Monolithic Integrated Circuits”, IEEE Proc. , Vol. 52,no. 12, p. 1537-1545.
3. Seeds, R. B., 1967a, “Yield and Cost Analysis of Bipolar LSI”, IEEE International Electron Meeting, p.12, Oct. , Washington, D.C..
4. Seeds, R.B., 1967b, “Yield, Economic, and Logistic Models for Complex Digital Arrays”, IEEE International Convention Record, Vol. 56, p. 61-66.
5. Cunningham, J. A., “The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing,” IEEE Trans. on Semiconductor Manufacturing, Vol. 3, No.2, May 1990, pp.60-71.
6. Maly, H.T.H.a.W., Interconnect yield model for manufacturability prediction insynthesis of standard cell based designs. Computer-Aided Design, 1996: p. 368-373.
7. Serda, M.Q.a.J., Semiconductor Manufacturing Technology. 2001: Prentice Hall.
1. 劉亭宜, GRNN 在晶圓製造裡良率模式之建構與分析, in 工業工程研究所. 2000, 元智大學.
2. 陳力行, NAND型Flash價格與交運量預測在風險分析下之決策模式, in 工業管理研究所. 2007, 中央大學.
3. 林董祥, 影響供應鏈夥伴關係相關因素之研究－以半導體供應鏈為例, in 資訊管理學系. 2000, 國立中央大學. p. 77.
4. 林瑞山, 類神經網路於預測晶圓測試良率之應用, in 工程管理所. 2004, 國立成功大學. p. 75.
5. 謝昆霖、唐麗英、謝仲杰, IC 多樣產品之生產線製造能力評估. 資訊管理研究, 2004(4).
6. 簡禎富、施義成、林振銘、陳瑞坤, 半導體製造技術與管理. 2005: 國立清華大學出版社.
7. 莊達人，2000，「VLSI 製造技術」，高立圖書有限公司，台灣。
8. 菊地正典, 圖解半導體－科技業的黑色煉金術. 2004: 世茂.
1. DRAMeXchange. DRAM晶片報價. 2008 2008/04/28 18:00 (GMT+8) [cited 2008 2008/04/28]; Available from: http://www.dramexchange.com/.
2. Wikipedia®. 十大建設. 2008 2008/02/24 [cited 2008 2008/04/28]; Available from: http://zh.wikipedia.org/w/index.php?title=%E5%8D%81%E5%A4%A7%E5%BB%BA%E8%A8%AD&variant=zh-tw.
3. Wikipedia®. 孫運璿先生生平. 2008 2008/04/20 [cited 2008 2008/04/28]; Available from: http://zh.wikipedia.org/w/index.php?title=%E5%AD%AB%E9%81%8B%E7%92%BF&variant=zh-tw.
4. 中央銀行. 中央銀行新台幣對美元銀行間成交之收盤匯率. 2008 2008/04/28 [cited 2008 2008/04/28]; Available from: http://www.cbc.gov.tw/foreign/fx/minfo_07_1.asp.
5. 天下雜誌. 天下雜誌一千大企業調查. [cited 2008 2008/05/17]; Available from: http://www.cw.com.tw/.
6. 時報周刊. 獨家專訪張忠謀－談孫運璿. 2006 [cited 2008 2008/05/17]; Available from: http://magazine.sina.com.tw/chinatimesweekly/1462/2006-02-28/ba4605.shtml.