博碩士論文 955201001 詳細資訊




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姓名 童偉程(Wei-Cheng Tung)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 具輸出級誤差消除機制之三位階三角積分D類放大器設計
(Design of a Tri-Level Sigma-Delta Class-D Amplifier with Output-Stage Error Cancellation Scheme)
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摘要(中) 本論文提出一種具輸出級誤差消除機制之三位階三角積分D類放大器設計。D類音頻放大器較傳統的AB類放大器具有高效能的優勢,然而音訊品質上, D類放大器輸出級開關採用脈衝寬度訊號控制,容易造成非線性時序誤差,使得輸出訊號的訊噪比降低。在降低非線性時序誤差方面,類比閉迴路式的脈衝邊緣延遲誤差校正(PEDEC)與雙向鋸齒波誤差校正(BSEC)為常見方式,主要原理是檢測輸出訊號誤差並回授去控制輸入訊號寬度。然此類方法電路中的低通濾波器及類比積分器的電阻與電容過大,造成電路積體化的困難,而使實現成本大幅增加。本論文以類比式脈衝誤差校正理論為基礎,提出一全數位化之誤差補償架構,使得整體D類放大器積體化可以達成並且大幅降低實現成本。此外,本論文將所提架構以三位階三角積分調變技術實現,使得輸出訊號品質更加提升。由模擬顯示,使用傳統類比誤差校正機制可將訊號總諧波(THD)自-30dB至-50dB區間壓抑至-50dB至-75dB左右。而使用本論文將所提架構可將訊號總諧波自-40dB至-70dB區間壓抑至-70dB至-90dB左右,最佳狀況更可至-100dB以下。以硬體實現成本而言,本論文所提架構較之傳統類比式架構電路面積可節省一半以上,並且無晶片外接元件。本論文所提架構在效能與成本上均具備優勢。
摘要(英) A tri-level sigma-delta class-D audio amplifier with output-stage error cancellation scheme is proposed in this thesis. The Class-D topology is superior to Class-AB one for its higher efficiency, however, nonlinear timing error on the output stage caused by the use of pulse-width modulation usually deteriorates output waveform quality. Conventional approaches proposed to solve the timing error problem are so called Pulse Edge Delay Error Cancellation (PEDEC) and Bi-directional Saw-tooth Error Cancellation (BSEC). Both approaches using output feedback to control the shape of input signal pulse. However, such analog correction methods need analog low pass filtering and integration functions with large resistor and capacitor values, preventing system being realized by integrated circuits. This thesis proposed an all-digital error cancellation scheme to overcome the aforementioned problems. By using tri-level sigma-delta modulation techniques, the performance of the proposed architecture can be further enhanced. Simulation results show that the total-harmonic-distortions of the proposed architecture can be suppressed from the range of -40dB and -70dB to -70dB and -90dB, compared to conventional analog approaches which are from the range of -30dB and -50dB to -50dB and -75dB. Furthermore, the circuit area of the proposed architecture is half of the analog approach, and without off-chip components.
關鍵字(中) ★ 誤差校正
★ 脈衝邊緣延遲
★ 雙向鋸齒波
★ D類放大器
★ 三角積分
關鍵字(英) ★ PEDEC
★ BSEC
★ Sigma-Delta
★ class-D
論文目次 第1章 簡介 1
1-1 功率放大器 2
1-1-1 Class A 2
1-1-2 Class B 3
1-1-3 Class AB 3
1-1-4 Class D 4
1-2 研究動機 5
1-3 論文組織 7
第2章 D類放大器工作原理介紹 8
2-1 脈衝寬度調變(PWM) 8
2-2 三角積分調變(SDM) 11
2-2-1 量化誤差(Quantization Error) 11
2-2-2 超取樣(Oversampling) 14
2-2-3 Σ-Δ調變器發展 15
2-3 Class D輸出級架構 26
第3章 D類放大器誤差校正架構設計 28
3-1 脈衝邊界延遲誤差校正(PEDEC) 28
3-1-1 PEDEC-基本原理 28
3-1-2 PEDEC-校正說明 31
3-1-3 PEDEC-限制條件 33
3-2 雙向鋸齒波誤差校正(BSEC) 34
3-2-1 BSEC-校正說明 34
3-2-2 BSEC、PEDEC分析比較 37
3-3 新的數位式誤差校正架構設計 39
第4章 新的數位式誤差校正架構之應用 44
4-1 1-bit & 1.5-bit Class D輸出級 44
4-1-1 1-bit輸出級 44
4-1-2 1.5-bit輸出級 45
4-2 1.5-bit數位式誤差校正架構設計 51
4-2-1 初步構思 51
4-3 1.5-bit數位式誤差校正架構 53
4-3-1 模擬結果 56
4-3-2 量化誤差 60
4-3-3 量化誤差的影響 61
第5章 結論 66
References 67
參考文獻 Reference
[1]Palumbo, G., “Understanding Delta-Sigma Data Converters,” Circuits and Devices Magazine, IEEE, Volume 22, Issue 4, Page(s):31 – 32, July-Aug. 2006.
[2]郭長佑, “「掌握」D類音效功率放大器(Class D Audio Power Amplifier)
音質與用電的新妥協方案,” DIGITIMES Inc., June 2005.
[3]Eric Gaalaas, Class D Audio Amplifiers: What, Why, and How, Analog Dialogue, Volume 40, June 2006.
[4]Nielsen, K., “Audio Power Amplifier Techniques With Energy Efficient Power Conversion,” Department of Applied Electronics, Building 451 Technical University of Denmark DK-2800 Lyngby, Volume I, Chapter 2, April 30, 1998.
[5]Temes, G. C.;Schreier, R.;Norsworthy, S. R., Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Circuits and Systems Society, October 1996.
[6]Temes, G. C.;Candy, J. C, Oversampling Delta-Sigma Data Converters, : Theory, Design, and Simulation, IEEE Circuits and Systems Society, September 1991.
[7]R. Carley; R. Schreier; G. Temes, “Delta-sigma ADCs with multi-bit internal converters,” : Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Press, New York, NY, 1997.
[8]David Johns; Ken Martin, Analog CMOS Integrated Circuit Design, John Wiley and Sons, 1997.
[9]R. Geiger, P. Allen; N. Strader, VLSI Design Techniques for Analog and Digital Circuits, Chapter 8. McGraw-Hill Publishing Inc., New York, NY, 1990.
[10]Mark Burns and Gordon W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, Oxford University Press, 2001.
[11]Stikvoort, E.F, "Some remarks on the stability and performance of the noise shaper or sigma-delta modulator," Communications, IEEE Transactions on Volume 36, Issue 10, Oct. 1988.
[12]Schreier, R, “An empirical study of high-order single-bit delta-sigma modulators,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 40, Issue 8, Page(s):461 – 466, Aug. 1993.
[13]Smedley, K.M., “Digital-PWM Audio Power Amplifiers with Noise and Ripple Shaping.,” Power Electronics Specialists Conference, PESC '94 Record., 25th Annual IEEE, Page(s):566 - 570 vol.1, 20-25 June 1994.
[14]Logan, S.; Hawksford, M.O.J, “Linearization of Class D Output Stages For High Performance Audio Power Amplifiers,” Advanced A-D and D-A Conversion Techniques and their Applications, Page(s):136 – 141, 6-8 Jul 1994
[15]Nielsen, K., “Pulse Edge Delay Error Correction (PEDEC) - A Novel Power StageError Correction Principle for Power Digital-Analog Conversion,” 103rd Convention of the AES. September 1997. New York. Preprint 4602.
[16]Nielsen, K., “ PEDEC - A Novel Pulse Referenced Control Method for High Quality Digital PWM Switching Power Amplification,” Power Electronics Specialists Conference, 1998. PESC 98 Record. 29th Annual IEEE, Volume 1, Page(s):200 – 207, 17-22 May 1998.
[17]Jong-hu Park; Kim, C.G.; Jae-hoon Jeong; Cho, B.H., “A novel controller for switching audio power amplifier with digital input,” Power Electronics Specialists Conference, 2002. pesc 02. 2002 IEEE 33rd Annual, Volume 1, Page(s):39 – 44, 23-27 June 2002.
[18]H. Inose, Y. Yasuda and J. Murakami, “A Telemetering System by Code Modulation--△-Σ Modulation,” IRE trans. On Space Electronics and Telemetry, vol. SET-8, pp. 204-209, Sep. 1962.
[19]W. Schweber, Electronic Communication Systems, Prentice-Hill, Inc., 4th ed.,2002.
[20]林裕修, “Novel Three-Level Modulation Technique for A Class-D Audio Amplifier,” 國立中山大學電機工程學系, July 2003.
[21]曾明鴻, “Sliding-Mode Quantization Theory with Applications to Controller Designs of a Class-D Amplifier and a Synchronous Buck Converter.,” 國立中山大學電機工程學系, July 2004.
[22]陳鏗元, “A Full-Bridge Class-D Amplifier Using Sigma Delta Modulation,” 國立交通大學電機與控制工程研究所, July 2003.
[23]林岑思, “A Full-Bridge Class-D Amplifier Using Finite Receding Horizon Quadratic Optimal Control,” 國立交通大學電機與控制工程研究所, July 2003.
[24]Class D Audio Amplifier, Analog Dialogue 40-60, June 2006, www.analog.com
指導教授 蔡佩芸、蘇純賢
(Pei-Yun Tsai、Chun-Hsien Su)
審核日期 2008-11-15
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