結合等化與同步雙迴路架構之數位電視廣播接收機

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姓名

龎嘉佑(Jia-you Pang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

結合等化與同步雙迴路架構之數位電視廣播接收機
(DVB OFDM Receiver Design Based on Joint Equalization and Synchronization Dual-Loop Architecture)

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摘要(中)

數位電視廣播(DVB-T)在台灣將成為未來無線電視的標準規格。因此，未來對數位電視接收機的需求必將大增。本論文針對DVB-T的標準設計一基頻內接收機。內接收機所要考慮的問題有符碼邊界偏移、載波頻率偏移和取樣時脈偏移等同步問題。除此之外還有通道效應的估測和資料回復的等化問題。在本論文中將一一提出上述問題的解決方法，並提出結合載波同步與等化雙迴路架構的演算法同時解決剩餘載波頻率偏移和通道等化的問題。最後設計硬體架構實現各個演算法電路，和傳統的演算法相比可提升系統效能並節省60%的記憶體。

摘要(英)

The European terrestrial broadcasting standard DVB-T has been adopted an official digital TV specification in Taiwan. As a result, the demand for DVB-T receiver will be heightened in the future. In this thesis, we will propose a joint carrier synchronization and equalization algorithm and implement hardware architecture for DVB-T baseband inner receiver. The OFDM inner receiver design should take account of synchronization issue, such as symbol boundary, carrier frequency offset and sampling frequency offset. In addition, the design must also take channel estimation and equalization issues into account. The proposed joint carrier synchronization and equalization algorithm can compensate both carrier frequency offset and channel frequency response at the same time. Finally, we will design the hardware architectures to realize the proposed algorithms. Comparing with the traditional methods, the proposed algorithm can promote the system performance and reduce above 60% storages.

關鍵字(中)

★ 同步電路
★ 數位電視廣播
★ 等化電路

關鍵字(英)

★ equalization
★ synchronization
★ DVB-T

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章緒論 1
1.1 研究動機 1
1.2 正交分頻多工(OFDM)調變簡介 1
1.2.1 OFDM 之數學模型 2
1.2.2 保護區間與循環前置碼 3
1.3 DVB-T系統規格簡介 4
1.3.1 傳輸模式2K 和 8K比較 4
1.3.2 參考訊號 6
1.4 論文架構 6
第二章 DVB-T同步架構設計 7
2.1 傳送/接收端非理想同步效應 7
2.1.1 符碼邊界偏移效應 7
2.1.2 載波頻率偏移效應 8
2.1.3 取樣時脈偏移效應 10
2.2 非理想同步效應估測 13
2.2.1 符碼邊界偏移估測 13
2.2.2 載波頻率偏移估測 14
2.2.3 取樣時脈偏移估測 18
2.3 同步硬體架構 19
2.3.1 符碼邊界偏移和分數型載波頻率偏移估測架構 20
2.3.2 整數型載波頻率偏移架構 23
2.3.3 取樣時脈偏移架構 25
第三章 DVB-T等化架構設計 26
3.1 2×1D通道估測和頻域等化器 26
3.1.1 通道頻率響應之時間方向內插 27
3.1.2 通道頻率響應之頻率方向內插 29
3.2 LMS頻率等化器 30
3.2.1 直角座標系LMS頻率等化器 31
3.2.2 極座標系LMS頻率等化器 32
3.3 結合載波同步與等化雙迴路架構設計 34
3.3.1 自動增益控制和載波回復等化器 34
3.3.2 結合載波同步與等化雙迴路架構 37
第四章電路架構設計與模擬結果 41
4.1 結合載波同步與等化雙迴路電路架構設計 41
4.1.1 雙迴路等化器電路操作模式設計 41
4.1.2 座標軸旋轉數位計算器(CORDIC)電路架構 43
4.1.3 數位內插器 46
4.1.4 CORDIC前置餘數電路 48
4.2 內接收機電路整合設計考量 49
4.2.1 同步和等化電路記憶體共用 49
4.2.2 極座標系相位方向內插 50
4.3 FPGA驗證 53
4.3.1 FPGA驗證平台 53
4.3.2 FPGA驗證結果 54
4.4 晶片佈局與模擬結果 58
4.4.1 晶片測試考量設計 58
4.4.2 晶片佈局結果 59
第五章結論與未來展望 61
參考文獻 62

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指導教授

薛木添(Muh-tian Shiue)

審核日期

2008-10-10

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