延伸考慮製程參數相關性之類比電路階層式變異數分析器

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姓名

李宜澄(Yi-Chen Lee) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

延伸考慮製程參數相關性之類比電路階層式變異數分析器
(An Extended Hierarchical Variance Analyzer with Consideration of Process Parameter Correlations for Analog Circuits)

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摘要(中)

隨著半導體製程技術進入深次微米時代，製程變動對於電路效能的影響愈來愈嚴重。因著製程變動已被觀察到存在著空間相關性，我們需要高速且可考慮製程變動相關性的方法使得我們可以更準確的估計電路效能參數的變動並且減少設計疊代成本。我們提出一個可計算類比電路各階層參數變異數之高速階層變異數分析方法的延伸架構，使之可考慮製程變動的相關性。我們提出兩個方法來實現這個分析器：1) 在製程層下建構一個虛擬層，以及2) 在原本的統計模型上加上第二個修正項。實驗結果顯示任一種方式實現出來的分析器皆達到出色的精準度及效率。

摘要(英)

As the technology scales down to ultra-deep-submicron, the impact of process variations on circuit performance gains importance. For it has been observed that the process variations are spatially correlated, analysis with the consideration of process parameters correlations and high computational efficiency is needed to help estimating variations of circuit performance accurately and reducing the cost of design iteration. We present an extended scheme of a prior high speed hierarchical variance analysis method to calculate the variance of parameters at each hierarchical layer in analog circuits while taking process parameters correlations into account. The proposed analyzer is realized by two ways: 1) constructing an extended pseudo level below process-layout level and 2) adding a second correction term to the prior statistical model. Experiment results show that analyzer realized by either of the two ways achieves high computational accuracy and efficiency.

關鍵字(中)

★ 分析器
★ 容限分析
★ 類比電路
★ 相關性
★ 階層
★ 變異數
★ 製程變動

關鍵字(英)

★ Variance
★ Hierarchy
★ Tolerance Analysis
★ Process Variation
★ Consideration
★ Analog Circuits
★ Analyzer

論文目次

摘要 i
Abstract ii
Acknowledgments iii
Table of Contents iv
List of Figures vi
List of Tables viii
Chapter 1 Introduction 1
1.1 The Challenge from Process Variability in Ultra-deep-submicron Technologies 1
1.2 Process Variation Classification 2
1.3 Spatial Correlation 3
1.4 Statistical Tolerance Analysis 3
1.4.1 Monte Carlo Analysis 3
1.4.2 Hierarchical Variance Analysis 4
1.5 Motivation 4
1.6 Organization of this Thesis 5
Chapter 2 Definitions and Theories of Statistics 6
Chapter 3 Prior Tolerance Analysis Approaches 12
3.1 Monte Carlo Analysis 12
3.2 Hierarchical Variance analysis 15
3.2.1 Modeling the System Behavior 15
3.2.2 Composition of Variances at Intermediate Hierarchical Nodes 16
3.2.3 Statistical Modeling 18
Chapter 4 The Proposed Analyzer Considering Process Parameter Correlations 20
4.1 The First Proposed Method: Construct a Pseudo Hierarchical Layer 20
4.1.1 The Proposed Hierarchy for Analog Circuits 20
4.1.2 Mathematical Analysis 21
4.1.3 Algorithm to Construct the Pseudo Hierarchical Layer 23
4.2 The Second Proposed Method: Modify the Model 27
4.2.1 Derivation of the Modified Model 28
Chapter 5 Evaluation of the Proposed Methods 31
5.1 Experiment Setup 31
6.1.1 Setup of Monte Carlo Analysis 32
5.1.2 Setup of Hierarchical Variance Analysis 34
5.1.3 Setup of the Proposed Analyzer 35
5.2 Experimental Results 36
5.2.1 Accuracy of Variance Calculation 36
5.2.2 Efficiency of Variance Calculation 39
5.2.3 Performance of the Approximation Algorithm 40
Chapter 6 Conclusions 43
Reference 44

參考文獻

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指導教授

陳竹一(Jwu-E Chen)

審核日期

2008-7-17

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