| 摘要(英) |
When semiconductor technology further scales into nanometer era, I/O-pad counts increase continually due to more and more function in chip. The locations of I/O pads not only affect the package design, but also change the noise inside the core. The traditional approaches solve these problems in package design flow and physical design flow respectively, which may have time-consuming and over-design problems. Using chip-package co-design method in pad assignment stage may be a practical approach to simultaneously solve these problems. A good pad assignment can improve the routing quality in packages and reduce the IR-drop in cores, which may solve the over-design problem and shorter the design cycle, too.
In this thesis, a chip-package co-design approach is proposed to reduce the routing congestion in packages. A pad switching algorithm is also proposed to control the routing congestion in packages and the IR-drop in cores at the same time. The experimental results of this work are encouraging. Compared with different approaches, our methodology reduces the routing congestion in packages and the IR-drop in cores simultaneously in all test circuits. |
| 參考文獻 |
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