應用於交換電容ΔΣ調變電路之電容排列良率自動化擺置平台

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黃健智(Chien-Chih Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於交換電容ΔΣ調變電路之電容排列良率自動化擺置平台
(Yield-aware Automatic Layout Placement via Capacitance Correlation for Switching-Capacitor Sigma-Delta Modulators)

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摘要(中)

進入深次微米的時代後，製程解析度快速縮小到比光學微影技術的光波波長還小時，製程的誤差將會越來越顯著且含有許多統計分佈的特性。伴隨著製程變動已被觀察到存在著空間相關性，因此，我們提出一套設計流程並應用於交換電容式的ΔΣ調變電路中的電容排列，此流程包含 1) 萃取各電容彼此的相關性 2) 依其相關性來決定各電容在實體佈局上的相對位置 3) 結合良率分析於實體佈局的決定。最後，發展為自動化設計平台可提供使用者良善的使用介面與降低設計上的複雜性。

摘要(英)

The process variations increase with the advance of semiconductor manufacturing, and consequently influence the circuit parameters. Due to the device dimensions shrinking and the wafer sizes increasing, the intra-die variations are becoming dominant and strongly layout dependent. In this work, the correlations with each design parameters are extracted firstly and they are used as the guideline for layout placement. A flow procedure is proposed for determining the corresponding positions for each target parameters, which are implemented by the conjunctions of proper number of units. Experimentally, the procedure is applied to the placement of capacitances for switching-capacitor sigma-delta modulators. The result shows that the circuit yield can be enhanced further more by considering the correlation into placement. For analog and mixed-signal circuits, an automatic layout platform can greatly reduce the design complexity, in turn, speed-up the time spent for iteration, and further improve the yield.

關鍵字(中)

★ 自動化
★ 良率分析

關鍵字(英)

★ Automatic Layout Placement
★ Yield

論文目次

摘要 i
Abstract ii
誌謝 iii
Table of Contents iv
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
Chapter 2 Basic Definition of Statistics 5
2.1 Mean, variance and standard deviation 5
2.2 Covariance and correlation 6
2.3 Normal distribution 7
Chapter 3 Variation Classification and Model Definition 10
3.1 Process-Variation Classification 10
3.2 The Model of Spatial Correlation 12
Chapter 4 Correlation Extraction and Placement Realization 15
4.1 The Extraction of Parameters’ Correlation 15
4.2 Placement Realization 18
4.2.1 Global Placement 19
4.2.2 Detail Placement 22
4.2.3 Auto Placement and Route on Laker Platform 23
Chapter 5 Experiment Results 25
5.1 Sigma-Delta Modulator Design 25
5.2 The Automatic Platform 26
5.3 Comparison 32
Chapter 6 Conclusions and Future Work 35
6.1 Conclusions 35
6.1 Future Work 35
Reference 36

參考文獻

[1] Director SW, Feldmann P, Krishna K. “Statistical integrated circuit design,” IEEE Journal of Solid-State Circuits, vol. 28, Iss. 3, 1993pp. 193-202.
[2] X. Jinjun, V. Zolotov, and H. Lei, “Robust Extraction of Spatial Correlation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, Iss.4, April 2007, pp. 619-631.
[3] Ripp A, Buhler M, Koehl J, Bickford J, Hibbeler J, Schlichtmann U, et al. “DATE 2006 special session: DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design,” Design, Automation and Test in Europe, 2006 DATE '06 Proceedings. vol. 1, 2006, pp. 1-6.
[4] Po-Hung Lin, Shyh-Chang Lin. “Analog placement based on novel symmetry-island formulation,” ACM/IEEE Design Automation Conference, July 2007, pp. 465-70.
[5] Qiang Ma, Young EFY, Pun KP. “Analog placement with common centroid constraints,” IEEE/ACM International Conference on Computer-Aided Design, 2007 pp. 579-85.
[6] Helmut E. Gracb, “Analog design centering and sizing,” Springer, 2007.
[7] Luo J, Sinha S, Su Q, Kawa J, Chiang C. “An IC manufacturing yield model considering intra-die variations,” ACM/IEEE Design Automation Conference, 2006 pp. 749-54.
[8] Stine BE, Boning DS, Chung JE. “Analysis and decomposition of spatial variation in integrated circuit processes and devices,” IEEE Transactions on Semiconductor Manufacturing, vol. 10, Iss. 1, 1997 pp. 24-41.
[9] P. M. Aziz, H. V. Sorensen, “An overview of sigma-delta converters,” IEEE Signal Processing Magazine, vol. 68, No. 1, January 1996, pp. 61-84.
[10] L. Yao, “A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm MOS,” IEEE Journal of Solid-State Circuit, vol. 39, No. 11, Nov. 2004, pp. 1809-1818.
[11] Y. F. Huang, “Iterative Optimization of Spatial Correlation for Switch-Capacitor Delta-Sigma Modulator,” master’s thesis, Dept. Electrical Engineering, Chung-Hua University, Hsinchu, 2006.
[12] L. P-W., C. J-E., W. C-L , C J-J, C L-C, and W. W-C, ”Design Methodology of
Analog/Mixed-Signal Circuits For Yield Enhancement,” IEEE European Test Symposium, 2008
[13] Ronald E. Walpole, Raymond H. Myers, Sharon L. Myers, Keying Ye. “Probability & Statistics for Engineers & Scientists,” 7th, Prentice Hall.
[14] Stuart, A and Ord, J. K. “Kendall’s Advanced Theory of Statistics,” Vol. 1 (5th ed.), New York: Oxford University Press 1987, pp. 320-325.

指導教授

陳竹一(Jwu-E Chen)

審核日期

2008-7-14

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