 |
|
|
|
以作者查詢圖書館館藏 、以作者查詢臺灣博碩士 、以作者查詢全國書目 、勘誤回報 、線上人數：26 、訪客IP：3.129.216.30
姓名 陳致均(Chih-Chun Chen) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 自我對準電極鍺量子點單電子/電洞電晶體之製作與特性分析
(The Fabrication and Electrical Characterization of Germanium QD Single Electron/Hole Transistor with Self-aligned Electrode)相關論文 檔案 [Endnote RIS 格式]
[相關文章]
[文章引用]
[完整記錄]
[館藏目錄]
[檢視]
- 本電子論文使用權限為同意立即開放。
- 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
- 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中) 近三十年來，半導體業不斷地追求更高的元件密度與更快的操作速度，為了
達到這兩個目的，金氧半場效電晶體( Metal Oxide Semiconductor Field Effect
Transistor，MOSFET )的通道長度不斷地向下微縮。在西元2008 年，Intel 已經
成功的發展出通道長度僅有35 nm 的MOSFET。儘管Intel 成功地不斷將通道向
下微縮，但微縮的過程是愈來愈艱辛。物理學家更大膽的預期MOSFET 通道微
縮的終點將止於約10 nm，因為這個尺度下的通道長度只有幾個原子直徑，造成
場效電晶體的微縮面臨瓶頸。為了繼續將元件尺寸向下微縮，達到更小面積、更
高操作速度的半導體元件，近年來量子元件的研究如雨後春筍般的出現。
在此篇論文中，著重於改善本實驗室上一代自我對準電極SET/SHT 在奈米
線( nanowire )蝕刻時良率不高、穿隧接面厚度過厚與源極與汲極摻雜濃度不足等
缺點。本論文成功的克服奈米尺度下蝕刻SOI wafer ( silicon on insulator ) 側蝕嚴
重的問題，大幅改善蝕刻時的良率，並在電性量測上觀察到由不對稱穿隧接面所
造成的兩個截然不同的ID-VG 譜線( spectrum )，且更深入探討量子點內的量子效
應。摘要(英) In the recent thirty years, the semiconductor industries pursue higher density of
devices and operation speed without end. In order to achieve these goals mentioned
above, the reductions of channel lengths of MOSFET are shorten incessantly. In 2008,
Intel has announced they developed the 35 nm gate length of MOSFET successfully.
Although they succeeded in decreasing the critical dimension, the develop procedure
has been much more difficult than before. The end of the channel length shortening is
expected to be 10 nm by physicists. Because the dimension of channel length is only
several times of an atomic diameter, the reason causes the bottleneck appearing in the
road of critical dimension shortening. In order to short the device dimension, speed up
operation speed, and decrease device area, the research of quantum devices are
published very often.
This thesis focuses on rising the low yield in nanowire etching, decreasing the
tunneling barrier thickness and solving the source/drain lack of dopant issue. Thisthesis has conquered the tremendous lateral etching issue under etching SOI wafer in
nanoscale. The characterizations of asymmetric tunneling barrier are observed
obviously under room-temperature.關鍵字(中) ★ 量子點
★ 單電子電晶體關鍵字(英) ★ SET
★ single electron transistor論文目次 目錄
中文摘要 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ i
英文摘要 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ ii
誌謝 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ iv
目錄 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ v
圖目錄 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ viii
第一章 簡介與研究動機‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 01
1 - 1 半導體元件的發展史……………………………………………… 01
1 - 2 單電子電晶體的誕生……………………………………………… 02
1 - 3 研究動機…………………………………………………………… 03
1 - 4 單電子電晶體的應用……………………………………………… 05
第二章 單電子/電洞電晶體之操作原理‧‧‧‧‧‧‧‧‧ 12
2 - 1 基本概念…………………………………………………………… 12
2 - 2 固定VG、調變VDS………………………………………………… 14
2 - 3 調變VG、固定VDS………………………………………………… 16
2 - 4 元件參數之萃取…………………………………………………… 17
第三章 元件關鍵製程開發與製作流程‧‧‧‧‧‧‧‧‧ 27
3 - 1 Si 對SiO2 具有高選擇比與垂直輪廓之乾蝕刻…………………… 27
3 - 2 電極自我對準量子點之技術……………………………………… 34
3 - 3 鍺量子點的形成…………………………………………………… 35
3 - 4 元件完整製作流程………………………………………………… 37
I 單晶矽鍺薄膜沉積…………………………………………… 37
II 複晶矽鍺薄膜沉積與離子佈植……………………………… 38
III 定義主動區 ………………………………………………… 38
IV 定義nanogap………………………………………………… 39
V 定義nanowire ……………………………………………… 40
VI TEOS oxide、Si3N4 spacer 的形成 ………………………… 40
VII 氧化poly-Si / c-SiGe /c-Si 形成穿隧位障與鍺量子點……… 41
VIII 複晶矽沉積與離子佈植……………………………………… 41
IX 後段製程 …………………………………………………… 42
第四章 元件電特性分析與製程討論‧‧‧‧‧‧‧‧‧‧ 60
4 - 1 量測儀器與方法…………………………………………………… 60
4 - 2 單電子電晶體之電性分析………………………………………… 61
I 汲極調變下之電流曲線 ……………………………………… 61
II 閘極調變下之電流曲線 ……………………………………… 61
4 - 3 單電洞電晶體之電性分析………………………………………… 63
I 汲極調變下之電流曲線 ……………………………………… 63
II 閘極調變下之電流曲線 ……………………………………… 67
4 - 4 元件分析與討論…………………………………………………… 74
第五章 總結與未來展望 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 86
參考文獻 91參考文獻 [1] 陳啟東，「單電子電晶體簡介」，物理雙月刊，第二十六卷，第三期，483－490頁，2004年6月。
[2] M. Saitoh, H. Harata and T. Hiramoto, “Room-temperature demonstration of integrated silicon single-electron transistor circuit for current switching and analog pattern matching,” in IEDM Tech Dig. 2004, p. 187.
[3] L. Zhuang, L. Guo and S. Y. Chou, “Silicon single-electron quantum-dot transistor switch operating at room-temperature,” Appl. Phys. Lett., vol. 72,
p. 1205, 1998.
[4] H. Ishikuro and T. Hiramoto, “Quantum mechanical effects in the silicon quantum dot in a single-electron transistor,” Appl. Phys. Lett., vol. 71, p. 3691, 1997.
[5] B. H. Choi et al., “Fabrication and room-temperature characterization of a silicon self-assembled quantum-dot transistor,” Appl. Phys. Lett., vol. 73, p. 3129, 1998.
[6] Y. Ono et al., “Fabrication method for IC-oriented Si twin-islanld single-electron transistors,” in IEDM Tech Dig. 1998, p. 147.
[7] P. W. Li et al., ”Fabrication of a germanium quantum-dot single-electron transistor with large coulomb-blockade oscillations at room-temperature,” Appl. Phys. Lett., vol. 85, p. 1532, 2004.
[8] G. L. Chen et al., “Tunneling spectroscopy of a germanium quantum dot in single-hole transistors with self-aligned electrodes,” Nanotechnol., vol. 18,
p. 475402, 2007.
[9] Y. Takahashi et al., “Silicon single-electron devices and their applications,” in IEEE Int. Symp. ISMVL, 2000, p. 411.
[10] J. Weis et al., “Transport spectroscopy of a confined electron system under a gate tip”, Phys. Rev. B, vol. 46, p. 12837, 1992.
[11] R. Westerman, D. Johnson and S. L. Lai, “ Notch-free etching of high aspect SOI structures using alternating deposition and etching and pulsed plasma,“ U.S. Patent 6905626, 2005.
[12] Enhanced SOI capability, Surface technology system, [online]. Available：http://www.stsystems.com
[13] D. Hisamoto et al., “FinFET – a Self-aligned double-gate MOSFET scalable to 20 nm”, IEEE Trans. Electron Device, vol. 47, p. 2320, 2000.
[14] H. K. Liou et al., “Effect of Ge concentration on SiGe oxidation behavior”, Appl. Phys. Lett., vol. 59, p. 1200, 1991.
[15] P. W. Li, W. M. Liao and S. W. Lin, ”Formation of atomic-scale germanium quantum dots by selective oxidation of SiGe/Si-on-insulator,” Appl. Phys. Lett., vol. 83, p. 4628, 2003.
[16] W. T. Lai and P. W. Li, “Growth kinetics and related physical/electrical properties of Ge quantum dot formed by thermal oxidation of Si1-xGex-on-insulator, ” Nanotechnol., vol. 18, p. 145402, 2007.
[17] P. W. Li et al., “Study of tunneling currents through germanium quantum-dot single-hole and -electron transistors,” Appl. Phys. Lett., vol. 88, p. 213117, 2006.
[18] M. Saitoh and T. Hiramoto, ”Room-temperature observation of negative differential conductance due to large quantum level spacing in silicon single-electron transistor,” Jpn. J. Appl. Phys., vol. 43, p. L210, 2004.
[19] K.C. Lu et al., “Point contact reactions between Ni and Si nanowires and reactive epitaxial growth of axial nano-NiSi/Si,” Appl. Phys. Lett., vol. 90,
p. 253111, 2007.
[20] W. T. Lai, David M. T. Kuo and P. W. Li, “Transient current through a single germanium quantum dot at room temperature,” Appl. Phys. Lett., to be published.指導教授 李佩雯(Pei-Wen Li) 審核日期 2008-7-25 推文 plurk
funp
live
udn
HD
myshare
netvibes
friend
youpush
delicious
baidu
網路書籤 Google bookmarks
del.icio.us
hemidemi
facebook
twitter
google
reddit