博碩士論文 955201055 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:13 、訪客IP:44.192.26.60
姓名 吳佳緯(Chia-wei Wu)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 鍺奈米線與矽奈米線電晶體之研製
(Fabrication and Study of Germanium Nanowire and Silicon Nanowire Transistors)
相關論文
★ 高效能矽鍺互補型電晶體之研製★ 高速低功率P型矽鍺金氧半電晶體之研究
★ 應變型矽鍺通道金氧半電晶體之研製★ 金屬矽化物薄膜與矽/矽鍺界面反應 之研究
★ 矽鍺異質源/汲極結構與pn二極體之研製★ 矽鍺/矽異質接面動態啓始電壓金氧半電晶體之研製
★ 應用於單電子電晶體之矽/鍺量子點研製★ 矽鍺/矽異質接面動態臨界電壓電晶體及矽鍺源/汲極結構之研製
★ 選擇性氧化複晶矽鍺形成鍺量子點的光特性與光二極體研製★ 選擇性氧化複晶矽鍺形成鍺量子點及其在金氧半浮點電容之應用
★ 量子點的電子能階★ 鍺量子點共振穿隧二極體與電晶體之關鍵製程模組開發與元件特性
★ 自對準矽奈米線金氧半場效電晶體之研製★ 鍺浮點記憶體之研製
★ 利用選擇性氧化單晶矽鍺形成鍺量子點之物性及電性分析★ 應用於數位電視頻帶之平衡不平衡轉換器設計
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 近四十年來,半導體業界不斷微縮(downscale)金氧半場效電晶體(metal-oxide-semiconductor field-effect-transistor,MOSFET)的尺寸,以達到高操作速度、高元件密度的目標。然而,元件尺寸並不可能無止盡地微縮下去,在微縮到30奈米以下時,嚴重的短通道效應(short channel effects)以及微縮閘介電層厚度所引起的漏電流會增加元件的靜態消耗功率,甚至會使元件完全失去功能。由奈米線或奈米管所建構的一維元件因為具有較低的技術風險,而被認為最有機會取代原有的矽科技。其中,鍺奈米線電晶體具有較高的通道載子遷移率,且量子效應可以更加提升載子的遷移率,再配合高介電係數介電層的使用,更可以提高閘極的控制能力,因此是一種相當具有前景的電晶體元件。
本論文提出了利用選擇性氧化矽鍺細線的方式形成鍺奈米線,除了完全與CMOS製程相容外,形成的奈米線更可以自我對準到電極;此外,也利用實驗室先前開發仿鰭式場效電晶體的結構,製作出具有自我對準電極的矽奈米線電晶體,並量測元件的室溫及低溫電流特性,以作為之後製作鍺奈米線電晶體的基礎。
摘要(英) In the past four decades, semiconductor industrials keep downscaling the size of MOSFETs in order to achieve the goals of high operation speed and high device density. However, the reduction of device size won’t last forever. When transistors shrink into or below 30 nm regime, leakage current due to severe short channel effects and thin gate dielectric causes the increase of off-state power consumption, and consequently causes functionality failure. One-dimensional devices based on nanowires or nanotubes are considered the immediate successors to replace the traditional silicon technology with relatively low technological risk. Germanium nanowire transistor, which has higher carrier mobility and can be further enhanced by quantum confinement effect, is one of the most promising devices. In addition, the control of gate to channel can also be improved by using high-k dielectrics.
In this thesis, we propose a method of selectively oxidizing silicon-germanium wires to form germanium nanowires. The process is fully compatible to CMOS technology, and nanowires formed by this way can self-align to source/drain electrodes. Besides, we fabricate silicon nanowire transistors with self-aligned electrodes in FinFET-like structure and measure the current-voltage (I-V) characteristics under room-temperature and low-temperature. The results provide a information foundation for fabricating germanium nanowire transistors in the future.
關鍵字(中) ★ 奈米線電晶體 關鍵字(英) ★ nanowire transistor
論文目次 中文摘要 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ i
英文摘要 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ ii
誌謝 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ iv
目錄 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ v
圖表目錄 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ vii
第一章 簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1-1 半導體元件發展‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1-2 奈米線電晶體‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 2
1-3 鍺奈米線的優點‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 4
第二章 奈米線電晶體製作現況與實驗動機‧‧‧‧‧‧‧‧ 11
2-1 前言‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 11
2-2 電子束微影定義奈米線‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 11
2-3 化學合成奈米線‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 13
2-4 選擇性氧化矽鍺形成鍺奈米線‧‧‧‧‧‧‧‧‧‧‧‧ 17
第三章 選擇性氧化矽鍺形成鍺奈米線實驗‧‧‧‧‧‧‧‧ 27
3-1 前言‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 27
3-2 鍺奈米線尺寸估計‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 27
3-3 實驗流程‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 29
3-4 實驗結果與討論‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 31
第四章 矽奈米線電晶體製作與電性分析‧‧‧‧‧‧‧‧‧ 43
4-1 前言‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 43
4-2 元件製作流程‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 43
4-3 室溫量測‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 47
4-4 低溫量測‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 48
4-5 元件與製程討論‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 53
第五章 總結與未來展望‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 80
參考文獻 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 81
英文簡歷 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 85
參考文獻 [1] S. E. Thompson et al., “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, vol. 51, p. 1790, 2004.
[2] S. Y. Wu et al., “A 32nm CMOS low power SoC platform technology for foundry applications with functional high density SRAM,” in IEDM Tech. Dig. 2007, p. 263.
[3] R. Chau et al., “Silicon nano-transistors for logic applications,” Physica E: Low-dimensional Systems and Nanostructures, vol. 19, p. 1, 2003.
[4] B. Yu et al., “One-dimensional germanium nanowires for future electronics,” J. Clust. Sci., vol. 17, p. 579, 2006.
[5] S. E. Thompson et al., “In search of “forever,” continued transistor scaling one new material at a time,” IEEE Trans. Semicond. Manuf., vol. 18, p. 26, 2005.
[6] B. Yu and M. Meyyappan, “Nanotechnology: role in emerging nanoelectronics,” Solid-State Electron., vol. 50, p. 536, 2006.
[7] M. Heuser et al., “Fabrication of wire-MOSFETs on silicon-on-insulator substrate,” Microelectron. Eng., vol. 61-62, p. 613, 2002.
[8] Y. Cui et al., “High performance silicon nanowire field effect transistors,” Nano Lett., vol. 3, p. 149, 2003.
[9] N. Singh et al., “High-performance fully depleted silicon nanowire (diameter ≦ 5 nm) gate-all-around CMOS devices,” IEEE Electron Device Lett., vol. 27, p. 383, 2006.
[10] K. Saraswat et al., “High performance germanium MOSFETs,” Mater. Sci. Eng., B vol. 26, p. 242, 2006.
[11] T. Krishnamohan et al., “High-mobility low band-to-band-tunneling strained- germanium double-gate heterostructure FETs: simulations,” IEEE Trans. Electron Devices, vol. 53, p. 1000, 2006.
[12] T. Maeda et al., “High mobility Ge-on-insulator p-channel MOSFETs using Pt germanide schottky source/drain,” IEEE Electron Device Lett., vol. 26, p. 102, 2005.
[13] C. O. Chui et al., “Germanium MOS capacitors incorporating ultrathin high-k gate dielectric,” IEEE Electron Device Lett., vol. 23, p. 473, 2002.
[14] Y. Maeda, N. Tsukamoto and Y. Yazawa, “Visible photoluminescence of Ge microcrystals embedded in SiO2 glassy matrices,” Appl. Phys. Lett., vol. 59, p. 3168, 1991.
[15] D. Hisamoto et al., “FinFET—a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, p. 2320, 2000.
[16] Y. K. Choi, T. J. King and C. Hu, “Nanoscale CMOS spacer FinFET for the terabit era,” IEEE Electron Device Lett., vol. 23, p. 25, 2002.
[17] X. Sun et al., “Synthesis of germanium nanowires on insulator catalyzed by indium or antimony,” J. Vac. Sci. Technol. B, vol. 25, p. 415, 2007.
[18] Y. Y. Wu and P. D. Yang, “Direct observation of vapor-liquid-solid nanowire growth,” J. Amer. Chem. Soc., vol. 123, p. 3165, 2001.
[19] G. M. Cohen et al., “Nanowire metal-oxide-semiconductor field effect transistor with doped epitaxial contacts for source and drain,” Appl. Phys. Lett., vol. 90, p. 233110, 2007.
[20] L. Zhang, R. Tu and H. Dai, “Parallel core-shell metal-dielectric-semiconductor germanium nanowires for high-current surround-gate field-effect transistors,” Nano Lett., vol. 6, p. 2785, 2006.
[21] W. M. Weber et al., “Silicon-nanowire transistors with intruded nickel-silicide contacts,” Nano Lett., vol. 6, p. 2660, 2006.
[22] H. K. Liou et al., “Effect of Ge concentration on SiGe oxidation behavior,” Appl. Phys. Lett., vol. 59, p. 1200, 1991.
[23] P. W. Li et al., “Study of tunneling currents through germanium quantum-dot single-hole and -electron transistors,” Appl. Phys. Lett., vol. 88, p. 213117, 2006.
[24] W. T. Lai and P. W. Li, “Growth kinetics and related physical/electrical properties of Ge quantum dots formed by thermal oxidation of Si1-xGex-on-insulator,” Nanotechnol., vol. 18, p. 145402, 2007.
[25] P. W. Li et al., “Fabrication of a germanium quantum-dot single-electron transistor with large coulomb-blockade oscillations at room-temperature,” Appl. Phys. Lett., vol. 85, p. 1532, 2004.
[26] G. L. Chen et al., “Tunneling spectroscopy of a germanium quantum dot in single-hole transistors with self-aligned electrodes,” Nanotechnol., vol. 18, p. 475402, 2007.
[27] S. Cristoloveanu, “Introduction to silicon on insulator materials and devices,” Microelectron. Eng., vol. 39, p. 145, 1997.
[28] H. C. Casey, Jr., Devices for integrated circuits silicon and III-V compound semiconductors, John Wiley New York, 1999.
[29] S. M. Sze, Semiconductor devices, physics and technology, 2nd ed., John Wiley New York, 2001.
[30] J. P. Colinge et al., “Temperature effects on trigate SOI MOSFETs,” IEEE Electron Device Lett., vol. 27, p. 172, 2006.
[31] S. C. Rustagi et al., “Low-temperature transport characteristics and quantum- confinement effects in gate-all-around Si-nanowire N-MOSFET,” IEEE Electron Device Lett., vol. 28, p. 909, 2007.
[32] J. Kedzierski et al., “Extension and source/drain design for high-performance FinFET devices,” IEEE Trans. Electron Devices, vol. 50, p. 952, 2003.
指導教授 李佩雯、郭明庭
(Pei-wen Li、David Ming-ting Kuo)
審核日期 2009-1-19
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明