鍺奈米線與矽奈米線電晶體之研製

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姓名

吳佳緯(Chia-wei Wu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

鍺奈米線與矽奈米線電晶體之研製
(Fabrication and Study of Germanium Nanowire and Silicon Nanowire Transistors)

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摘要(中)

近四十年來，半導體業界不斷微縮(downscale)金氧半場效電晶體(metal-oxide-semiconductor field-effect-transistor，MOSFET)的尺寸，以達到高操作速度、高元件密度的目標。然而，元件尺寸並不可能無止盡地微縮下去，在微縮到30奈米以下時，嚴重的短通道效應(short channel effects)以及微縮閘介電層厚度所引起的漏電流會增加元件的靜態消耗功率，甚至會使元件完全失去功能。由奈米線或奈米管所建構的一維元件因為具有較低的技術風險，而被認為最有機會取代原有的矽科技。其中，鍺奈米線電晶體具有較高的通道載子遷移率，且量子效應可以更加提升載子的遷移率，再配合高介電係數介電層的使用，更可以提高閘極的控制能力，因此是一種相當具有前景的電晶體元件。
本論文提出了利用選擇性氧化矽鍺細線的方式形成鍺奈米線，除了完全與CMOS製程相容外，形成的奈米線更可以自我對準到電極；此外，也利用實驗室先前開發仿鰭式場效電晶體的結構，製作出具有自我對準電極的矽奈米線電晶體，並量測元件的室溫及低溫電流特性，以作為之後製作鍺奈米線電晶體的基礎。

摘要(英)

In the past four decades, semiconductor industrials keep downscaling the size of MOSFETs in order to achieve the goals of high operation speed and high device density. However, the reduction of device size won’t last forever. When transistors shrink into or below 30 nm regime, leakage current due to severe short channel effects and thin gate dielectric causes the increase of off-state power consumption, and consequently causes functionality failure. One-dimensional devices based on nanowires or nanotubes are considered the immediate successors to replace the traditional silicon technology with relatively low technological risk. Germanium nanowire transistor, which has higher carrier mobility and can be further enhanced by quantum confinement effect, is one of the most promising devices. In addition, the control of gate to channel can also be improved by using high-k dielectrics.
In this thesis, we propose a method of selectively oxidizing silicon-germanium wires to form germanium nanowires. The process is fully compatible to CMOS technology, and nanowires formed by this way can self-align to source/drain electrodes. Besides, we fabricate silicon nanowire transistors with self-aligned electrodes in FinFET-like structure and measure the current-voltage (I-V) characteristics under room-temperature and low-temperature. The results provide a information foundation for fabricating germanium nanowire transistors in the future.

關鍵字(中)

★ 奈米線電晶體

關鍵字(英)

★ nanowire transistor

論文目次

中文摘要 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ i
英文摘要 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ ii
誌謝 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ iv
目錄 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ v
圖表目錄 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ vii
第一章簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1-1 半導體元件發展‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1
1-2 奈米線電晶體‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 2
1-3 鍺奈米線的優點‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 4
第二章奈米線電晶體製作現況與實驗動機‧‧‧‧‧‧‧‧ 11
2-1 前言‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 11
2-2 電子束微影定義奈米線‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 11
2-3 化學合成奈米線‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 13
2-4 選擇性氧化矽鍺形成鍺奈米線‧‧‧‧‧‧‧‧‧‧‧‧ 17
第三章選擇性氧化矽鍺形成鍺奈米線實驗‧‧‧‧‧‧‧‧ 27
3-1 前言‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 27
3-2 鍺奈米線尺寸估計‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 27
3-3 實驗流程‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 29
3-4 實驗結果與討論‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 31
第四章矽奈米線電晶體製作與電性分析‧‧‧‧‧‧‧‧‧ 43
4-1 前言‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 43
4-2 元件製作流程‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 43
4-3 室溫量測‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 47
4-4 低溫量測‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 48
4-5 元件與製程討論‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 53
第五章總結與未來展望‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 80
參考文獻 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 81
英文簡歷 ‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 85

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指導教授

李佩雯、郭明庭
(Pei-wen Li、David Ming-ting Kuo)

審核日期

2009-1-19

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