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姓名	簡中彥(Chung-Yen Chien)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	選擇性氧化複晶矽鍺奈米結構形成鍺量子點及在單電子電晶體之應用 (Germanium quantum dots formed by selectively oxidizing poly-SiGe nano-structure for single electron transistor application)
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檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載] 本電子論文使用權限為同意立即開放。 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中)	從1985年單電子電晶體 (single electron transistor)的概念由莫斯科大學的兩位教授提出後，由於它的高操作速度、低消耗功率，以及有別於傳統元件的量子特性，使得單電子電晶體吸引了許多研究團隊的注意。近十年來，為了和CMOS 製程技術整合，以矽基 (silicon base)半導體製作的單電子電晶體，更如雨後春筍般地相繼發表。然而，這些元件都面臨了製程再現性、關鍵尺寸不易微縮，與製程花費昂貴等問題。 在本論文中，著重於改善本實驗室過去以低壓化學氣相系統 (low pressure chemical vapor deposition system)將複晶矽鍺沉積在絕緣層上碰到的沉積率太快、薄膜表面起伏過大，與薄膜中鍺含量過高等問題。此外，將複晶矽鍺應用到本實驗室早先開發的三端電極與鍺量子點自我對準的結構中，且佐以高解析度的穿透式電子顯微鏡觀察，提出選擇性氧化複晶矽鍺合金自我形成鍺量子點與穿隧接面的直接證據。根據穿透式電子顯微鏡影像，本論文觀察到，鍺量子的顆數與閘長度間具有很強的相依性。當閘長度小於40 nm 時僅會形成單一一顆鍺量子點，但當閘長度大於40 nm時，則會形成一顆或兩顆的鍺量子點。最後以電子顯微鏡影像搭配模擬對奈米結構的氧化過程進行分析。
摘要(英)	Since the first concept of single electron transistor (SET) was proposed by Likharev et al. in Moscow University at 1985, SETs have attracted a lot of attention due to their high speed, ultralow power consumption, and unique quantum characteristics. In decades, many researchers have developed the cutting-edge fabrication technology for silicon based SETs in complementary metal-oxide-semiconductor (CMOS) compatible processes. However, all these devices face the issue of reproducibility, scalability and high cost issues. The main theme of this thesis is to improve the process parameters such as deposition rate, surface roughness and germanium mole fraction of poly-SiGe on insulator using low pressure chemical vapor deposition (LPCVD) technique. Consequently, we could apply the developed poly-SiGe films into a self-aligned SET structure, which has been proposed and demonstrated. We have used transmission electron microscopy (TEM) to verify the existence and number of self-assembled germanium quantum dot and tunneling barriers widths. We found that only one Ge quantum dots embedded in oxide matrix when channel length less than 40 nm, while one or two Ge quantum dot(s) for the channel length larger than 40 nm. The results are well explained by simulated oxidation contour of nano-structure using T-suprem4.
關鍵字(中)	★ 單電子電晶體 ★ 自我對準結構 ★ 複晶矽鍺 ★ 選擇性氧化	關鍵字(英)	★ selective oxidation ★ poly-SiGe ★ seld-aligned structure ★ single electron transistor
論文目次	中文摘要 ………………………………………………………… i 英文摘要 ………………………………………………………… ii 誌謝 ………………………………………………………… iii 目錄 ………………………………………………………… iv 圖目錄 ………………………………………………………… vii 表目錄 ………………………………………………………… xi 第一章 研究動機與簡介……………………………… 01 1-1 半導體元件發展史…………………………………… 01 1-2 單電子電晶體的誕生………………………………… 02 1-3 研就動機……………………………………………… 03 第二章 量子點的形成………………………………………… 09 2-1 量子點材料…………………………………………… 09 2-2 量子點製作方式……………………………………… 09 2-3 以氧化的方式製作量子點…………………………… 10 2-4 量子點接觸…………………………………………… 11 2-5 算盤串珠狀奈米線…………………………………… 12 2-6 圖象相依氧化法……………………………………… 13 2-7 矽鍺選擇性氧化……………………………………… 14 第三章 複晶矽鍺薄膜沉積與低溫氧化………………… 23 3-1 前言…………………………………………………… 23 3-2 複晶矽鍺沉積條件開發……………………………… 24 3-2-1 複晶矽鍺沉積條件回顧……………………………… 24 3-2-2 沉積率與沉積溫度…………………………………… 25 3-2-3 薄膜鍺含量與沉積率………………………………… 26 3-2-4 沉積溫度與薄膜鍺含量……………………………… 27 3-2-5 鍺含量20 %複晶矽鍺沉積…………………………… 28 3-2-6 鍺含量10 % 複晶矽鍺沉積………………………… 28 3-2-7 鍺含量5 % 複晶矽鍺沉積…………………………… 29 3-3 複晶矽鍺氧化………………………………………… 31 3-3-1 前言…………………………………………………… 31 3-3-2 複晶矽鍺氧化實驗設計……………………………… 31 3-3-3 單晶矽氧化曲線運算………………………………… 32 3-3-4 複晶矽鍺氧化實驗結果與分析……………………… 34 第四章 鍺量子點與電極自我對準結構研製………………… 48 4-1 鍺量子點與三端電極自我對準結構製作…………… 48 4-2 自我對準結構之穿透式電子顯微鏡影像分析……… 50 4-2-1 閘長度與鍺量子點數目……………………………… 51 4-2-2 氧化前後露出奈米線長度的變化…………………… 52 4-2-3 氧化前後露出奈米線寬度的變化…………………… 53 4-2-4 複晶矽奈米電極的形狀……………………………… 57 4-3 三端電極與鍺量子點自我對準的ID-VG 量測譜線… 58 第五章 總結與未來展望……………………………………… 79 Reference………………………………………………………… 82 Biography ………………………………………………………… 88 Publication list………………………………………………… 89
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指導教授	李佩雯、郭明庭 (Pei-Wen Li、Ming-Ting Kuo)	審核日期	2009-1-19
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