應用於微波及毫米波鎖相迴路之金氧半場效電晶體注入鎖定振盪器研究

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葉彥良(Yen-Liang Yeh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於微波及毫米波鎖相迴路之金氧半場效電晶體注入鎖定振盪器研究
(Research on CMOS Injection-Locked Oscillators for Microwave and Millimeter-Wave Phase-Locked Loop)

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摘要(中)

本博士論文主要針對應用於微波與毫米波鎖相迴路之注入鎖定振盪器的研究與討論。首先，介紹注入鎖定的基本理論，並提出一個注入鎖定振盪器的相位雜訊模型，從理論分析可以得知，注入鎖定振盪器的輸出相位雜訊包含注入訊號的相位雜訊且為低通濾波響應、與注入鎖定振盪器本身之相位雜訊且為高通濾波響應。所提出的相位雜訊模型可應用於次諧波注入鎖定鎖相迴路、注入鎖定除頻器與注入鎖定倍頻器設計分析中。
第三章提出一個使用90奈米CMOS之W頻帶注入鎖定除三除頻器，並使用二階諧波增強的技術，在不需額外的直流功耗下，提升注入鎖定除頻器的鎖定範圍，所提出的架構有較小輸入電容，更適合整合至W頻帶鎖相迴路中。此外，本論文也提出一針對鎖定範圍的理論模型，從理論模型分析得知，鎖定範圍跟注入器(injector)的元件尺寸與注入訊號的大小成正比。藉由適當地選擇注入器的閘極偏壓可以獲得最大的鎖定範圍。成功設計W頻帶注入鎖定除三除頻器，在未使用可變電容調整頻率的情況下，量測注入鎖定除頻器的鎖定範圍從91.4至93.5 GHz，輸出功率皆大於–15 dBm，核心直流功耗為1.5 mW，供應電壓為0.7 V。另一方面，所提出的注入鎖定除三除頻器也成玏地整合至V頻帶鎖相迴路，使用製程為65奈米CMOS，操作頻率為58.5 GHz時，在偏移中心頻1 MHz處量測相位雜訊為–83.5 dBc/Hz，直流總功耗為44 mW。
在第四章提出一個具有低直流功耗與寬注入鎖定範圍之注入鎖定三倍頻器，藉由使用變壓器耦合的架構，此次提出的注入鎖定三倍頻器具有下列之優點：1) 與過去傳統的注入鎖定三倍頻器相比，由於沒有源級退化(source degeneration)，交叉耦合對(cross-coupled pair)所產生的負電阻不會減少，所以可以操作在低直流供應電壓與低功耗、2) 藉由適當選擇注入器的偏壓獲得最大化鎖定範圍、3) 利用阻抗轉換降低注入器的寄生電容、與4) 藉由選擇較大的元件尺寸，讓注入器產生更大的三階諧波功率。此外，採用多階共振腔再次提升操作頻率與鎖定範圍。接著，根據變壓器耦合架構，提出一個鎖定範圍的理論模型，並與實驗結果相互驗證。所提出的注入鎖定三倍頻器成功實現於90奈米CMOS，在未使用可變電容的情況下，量測注入鎖定三倍頻器之自由(free-running)振盪頻率為94.51 GHz。在注入功率為小於–1 dBm時，量測鎖定範圍為5.9 GHz，直流供應電壓與功耗分別為0.7 V與1 mW。
使用延遲鎖定迴路自我對準注入的技術，實現一個低抖動(jitter)與低相位雜訊10 GHz次諧波注入鎖定鎖相迴路。藉由此次提出的創新架構，讓注入訊號與壓控振盪器的輸出相位隨環境變異可以自動地對準，並進一步地降低抖動。發展出一套針對次諧波注入鎖定鎖相迴路的相位雜訊模型，藉由注入鎖定的技術，大幅改善次諧波注入鎖定鎖相迴路的中心頻雜訊，其中輸出相位雜訊的設計考量包含鎖定範圍與頻率除數。成功完成一個10 GHz之次諧波注入鎖定鎖相迴路，在操作頻率為10 GHz及偏移中心頻為1 MHz時，量測次諧波注入鎖定鎖相迴路之相位雜訊為–130.2 dBc/Hz，均方根值(rms)抖動44 fs，直流總功耗為62.7 mW。
最後，概括本論文所提出之研究成果，及未來可研究內容於第六章。

摘要(英)

This doctoral dissertation focuses on the injection-locked oscillators for the microwave and millimeter-wave phase-locked loop (PLL). The basic concept of the injection-locked theory is introduced in Chapter 2. A phase noise model for the injection-locked oscillator (ILO) is proposed for the design and analysis. The output phase noise of the ILO is contributed from the injection signal with the lowpass response and the inherent noise of the ILO with the highpass response. The phase noise model of the ILO can be also applied to the sub-harmonically injection-locked PLL (SILPLL), injection-locked frequency divider (ILFD), and injection-locked frequency multiplier.
A W-band divide-by-three ILFD in 90 nm CMOS process is presented in Chapter 3. Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, and the small input capacitance is more feasible for W-Band PLL integration. The locking range of the ILFD is investigated to obtain a theoretical model. From the analysis, the locking range is proportional to the device size of the injectors and the amplitude of the injection signal. In addition, the locking range can be enhanced with a proper gate dc bias of the injectors. The measured locking range of the proposed ILFD is from 91.4 to 93.5 GHz without varactor tuning, and the output power is higher than -15 dBm. The core dc power of the ILFD consumption is 1.5 mW with a supply voltage of 0.7 V. Furthermore, the proposed divide-by-three ILFD is also successfully integrated to a V-band PLL using 65 nm CMOS process. At an operation frequency of 58.5 GHz, the measured phase noise at 1 MHz offset is –83.5 dBc/Hz. The total dc power consumption of the PLL is 44 mW.
In Chapter 4, we proposed a W-band wide locking range injection-locked frequency tripler (ILFT) with low dc power consumption. By using a transformer coupled (TC) topology, the proposed TC-ILFT features the following advantages: 1) the negative resistance of the cross-coupled pair is not degraded due to the proposed TC-ILFT without source degeneration, and the TC-ILFT can be operated in lower dc supply voltage as compared to the conventional ILFTs, 2) the dc bias of the injector can be properly designed for maximizing locking range, 3) the parasitic capacitance provided by the injector can be reduced due to the impedance transformation, and 4) the larger device size of the injector can be chosen enhancing the third harmonic. Moreover, the operation frequency and the locking range are boosted using a multi-order resonator. A theoretical model of the proposed TC-ILFT is also established and it has been carefully verified with the experimental results. The free-running oscillation frequency of the proposed TC-ILFT is 94.51 GHz. As the input power is –1 dBm, the measured locking range is 5.9 GHz without varactor tuning. The dc supply voltage and the power consumption are 0.7 V and 1 mW, respectively.
A low jitter low phase noise 10-GHz SILPLL with delay-locked loop (DLL) self-aligned injection using 65 nm CMOS technology is presented in Chapter 5. With the proposed innovative topology, the phase between the injection signal and the sub-harmonically injection-locked voltage controlled oscillator (SILVCO) in the PLL can be dynamically aligned to minimize the jitter over the variation. A theoretical model for the SILPLL is developed for the design methodology, and the in-band phase noise of the SILPLL can be significantly improved using the SIL technique. The design considerations of the locking range and frequency division ratio are addressed. As the operation frequency is 10 GHz, the measured phase noise of the proposed SILPLL with self-aligned injection is –130.2 dBc/Hz at 1 MHz offset with a rms jitter of 44 fs. The total dc power consumption is 62.7 mW.
Finally, the conclusion and future works are given in Chapter 6.

關鍵字(中)

★ 注入鎖定
★ 鎖相迴路
★ 金氧半場效電晶體

關鍵字(英)

★ injection-locked
★ phase-locked loop
★ CMOS

論文目次

摘要 I
Abstract III
List of Figures IX
List of Tables XIII
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Literatures Survey 2
1.3 Contributions 6
1.4 Dissertation Organization 7
Chapter 2 Injection Locking and Pulling in Oscillator 9
2.1 Concept of Injection Locking [6] 9
2.1.1 Phase Shift in the LC tank 9
2.1.2 Locking Range Analysis 11
2.2 Injection Locking [6] 12
2.2.1 Quasi-Lock 14
2.2.2 Fast Beat 16
2.3 Phase Noise in Injection-Locked Oscillator 16
2.4 Summary 19
Chapter 3 Design and Analysis of a W-band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique 21
3.1 Introduction of Frequency Dividers 21
3.2 Circuit Topology 24
3.3 Locking Range Analysis 25
3.3.1 Quality Factor of The LC Tank 26
3.3.2 Injection and Oscillation Current 27
3.3.3 Locking Range 29
3.3.4 Layout Considerations of The Inductor 31
3.4 Circuit Design 33
3.5 Experimental Results and Discussions 36
3.6 Phase-Locked Loop Implementation with Proposed Divide-by-Three ILFD 39
3.6.1 Circuit Implementation of the V-band PLL 41
3.6.2 Experimental Results and Discussions of the V-band PLL 42
3.7 Performance Summary 44
Chapter 4 A W-band Wide Locking Range and Low DC Power Injection-Locked Frequency Tripler using Transformer Coupled Technique 47
4.1 Introduction of Frequency Multiplier 47
4.2 Circuit Design and Analysis 51
4.2.1 Negative Resistance Analysis 52
4.2.2 Phase Shift in the LC Tank and Locking Range Analysis 53
4.2.3 Injection through Transformer 57
4.2.4 Bias of the Injector 57
4.2.5 Device Size of the Injector 59
4.2.6 Frequency Boosting 61
4.2.7 Transformer Design 62
4.3 Experimental Results and Discussions 65
4.4 Performance Summary 70
Chapter 5 A Low Jitter Low Phase Noise 10-GHz Sub-Harmonically Injection-Locked PLL with Self-Aligned Injection in 65 nm CMOS Technology 73
5.1 Introduction of Conventional PLL 73
5.2 Sub-harmonically Injection-Locked PLL 75
5.3 Phase Noise Analysis of the SILPLL 78
5.4 Circuit Implementation 82
5.4.1 SILVCO and VCDL 83
5.4.2 Current-Mode-Logic Frequency Divider 84
5.4.3 Phase Detector and Frequency Detector 85
5.4.4 System Simulation for SILPLL 89
5.5 Measurement Results and Discussions 90
5.5.1 SILPLL without Self-Aligned Technique 90
5.5.2 SILPLL with Self-Aligned Technique 93
5.6 Performance Summary 96
Chapter 6 Conclusions 99
Reference 103
Publication List 115

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指導教授

張鴻埜(Hong-Yeh Chang)

審核日期

2013-5-28

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