博碩士論文 955201103 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:25 、訪客IP:54.210.158.163
姓名 黃盟元(Meng-yuan Huang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 陣列MiM電容的平衡接點之通道繞線法
(Balanced-Via Channel Routing for Array-type MiM Capacitors)
相關論文
★ E2T-iSEE:應用於事件與情感狀態轉移排程器之編輯★ “偶”:具情感之球型機器人
★ 陣列區塊電容產生器於製程設計套件之評量★ 應用於數位家庭整合計畫影像傳輸子系統之設計考量與實現
★ LED 背光模組靜電放電路徑★ 電阻串連式連續參考值產生器於製程設計套件之評量
★ 短篇故事分類與敘述★ 延伸考慮製程參數相關性之類比電路階層式變異數分析器
★ 以電子電路觀點對田口式惠斯登電橋模擬實例的再分析★ 應用於交換電容ΔΣ調變電路之電容排列良率自動化擺置平台
★ 陣列MiM電容的自動化佈局★ 氣象資訊達人
★ 嵌入式WHDVI多核心Forth微控制器之設計★ 應用於電容陣列區塊之維持比值良率的通道繞線法
★ 使用於矽穿孔耦合分析之垂直十字鏈基板結構★ 垂直十字鏈基板結構應用於矽穿孔雜訊評估
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中) 隨著半導體製程的縮小,製程變動的問題造成元件之間不匹配是日益嚴重。本論文提出Balanced-Via Channel Routing (BVCR)的繞線佈局法,可實現相關性電容的良率評估器所得到最佳佈局擺放,並依據既定的繞線方式達到所要求的元件匹配。BVCR遵照設計規則(Design rule)且著重於每個元件間的繞線的長度平衡。除此之外,BVCR的自動繞線機制可大幅降低佈局時間及人力成本,以加速產品上市的時效。
摘要(英) Devices mismatch is usually caused by the process variation. The uncontrollable process variation has become a severe problem as the semiconductor technology continues to shrink. We proposed the Balanced-Via Channel Routing (BVCR) to implement the optimum placement which generated by yield evaluator. Based on routing style of BVCR and design rules, the routing wires between devices can be balanced. Furthermore, the automatic system of BVCR can reduce the design costs and speed-up the time to market.
關鍵字(中) ★ 平衡接點之通道繞線法
★ 良率評估器
★ 空間相關性
★ 共質心
關鍵字(英) ★ yield evaluator
★ Balanced-Via Channel Routing
★ Common -Centroid
★ Spatial Correlation
論文目次 第一章 簡介 1
1-1前言 1
1-2論文組織 2
第二章 前置工作 3
2-1 電容基本概念 3
2-1-1 電容簡介 3
2-2 電容不匹配的原因和電容匹配規則 5
2-3共質心(COMMON CENTROID) 9
第三章 空間相關性和元件不匹配 12
3-1空間相關性(SPATIAL CORRELATION) 12
3-2相關性(CORRELATION)與元件不匹配(MISMATCH) 15
3-3電容比值(RATIO)的相關性(CORRELATION)與變異數(VARIANCE)16
第四章 電容擺置(CAPACITOR PLACEMENT) 20
4-1交換式電容(SWITCH CAPACITOR) 20
4-2三角積分調變器(SIGMA-DELTA MODULATOR) 22
4-3交換電容式濾波器(SWITCHED-CAPACITOR BIQUAD FILTER) 25
第五章 繞線 29
5-1電容佈局( CAPACITOR LAYOUT) 29
5-1-1 Design Rule 29
5-1-2 Balanced-Via Chanel Routing (BVCR) 29
5-2實驗流程 32
5-3 模擬結果 35
第六章 結論與未來工作 43
6-1結論 43
6-2未來工作 43
參考文獻 44
參考文獻 [1]A. Hastings and R. A. Hastings, The Art of Analog Layout, Prentice Hall, 2000.
[2]M. J. McNutt, S. LeMarquis and J. L. Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE Journal of Solid-State Circuits, Vol. 29 , No. 5, pp. 611-616, May 1994.
[3]C. S. G. Conroy, W. A. Lane and M. A. Moran, “Statistical Design Techniques for D/A Converters,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 4, pp. 1118-1128, Aug 1989.
[4]J.-E Chen, P.-W. Luo and C.-L. Wey, “Yield evaluation of analog placement with arbitrary capacitor ratio,” IEEE International Symposium on Quality of Electronic Design, pp. 179-184, Mar. 2009
[5]P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Oxford, 2002.
[6]B.E. Boser and B.A. Wooley, “The design of sigma-delta modulation analog-to-digital converters,” IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, pp. 1298–1308, Dec. 1988.
[7]P. M. Aziz, H. V. Sorensen and J. V. Spiegel, “An overview of sigma-delta converters,” IEEE Signal Processing Magazine, Vol. 68, No. 1, pp. 61–84, Jan. 1996.
[8]P.-W. Luo, J.-E Chen, C.-L. Wey, L.-C. Cheng, J.-J. Chen and W.-C. Wu, “Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 11, pp. 2097-2101 , Nov. 2008.
[9]Laker User Guide and Tutorial, Nov. 2003.
[10]Laker TCL Reference, Nov. 2003.
[11]Clif Flynt, Tcl/Tk :A Developer's Guide, Morgan Kaufmann,2003.
[12]B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill, 2001.
[13]M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, Vol. 24,No. 5, pp. 1433-1439, Oct 1989.
[14]D. Khalil, M. Dessouky, V. Bourguet, M. M. Louerat, A. Catheline, and H. Ragai, "Evaluation of Capacitance Ratios in Automated Accurate Cmmon-Centroid Capacitance Arrays," Proceedings of the 6th International Symposium on Quality of Electronic Design, pp. 143-147, Mar 2005.
指導教授 陳竹一(Jwu-E Chen) 審核日期 2009-7-22
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明