博碩士論文 955401001 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:7 、訪客IP:3.90.207.89
姓名 許源佳(Yuan-Chia Hsu)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用積體電路上方後製程與整合被動元件於互補式金氧半導體製程之系統封裝研究
(Study of System-in-Package Technology using Above-IC Post Process and Integrated Passive Device on CMOS Process)
相關論文
★ 應用於筆記型電腦數位電視單極天線之研製★ 應用於數位機上盒與纜線數據機之電纜多媒體傳輸標準多工濾波器
★ 印刷共面波導饋入式多頻帶與超寬頻天線設計★ 微波存取全球互通頻段前向匯入式功率放大器與高效率Class F類功率放大器暨壓控振盪器電路之研製
★ 應用於矽基功率放大器與混頻器之傳輸線型變壓器研究★ 應用於V-頻段射頻收發機前端電路之低功耗源極注入式混頻器之研製
★ 應用fT-倍頻電路架構於毫米波壓控振盪器與注入鎖定除頻器之研製★ 應用傳輸線型變壓器於X/K–Ka/V頻段全積體整合之寬頻互補式金氧半導體功率放大器研製
★ 應用於K / V 頻段低功耗混頻器之研製★ 應用於K/V頻段之低功耗CMOS低雜訊放大器之研究
★ 應用於5-GHz CMOS射頻前端電路之低電壓自偏壓式混頻器與高線性化功率放大器之研製★ 應用於 K 頻段射頻接收機之寬頻低功耗 CMOS 低雜訊放大器之研製
★ 應用磁耦合變壓器於K頻段之低功耗互補式金氧半導體壓控振盪器研製★ 應用於K頻段之單向化全積體整合功率放大器與應用於V頻段之寬頻功率放大器研製
★ 應用於C/X頻段全積體整合之互補式金氧半導體寬頻低功耗降頻器與寬頻功率混頻器之研製★ 應用於 5-11 GHz寬頻低雜訊放大器與5 GHz/11 GHz雙頻低雜訊放大器之研製
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中) 本篇論文主要研究系統封裝設計的實現方法,利用積體電路上方後製程與整合被動元件兩種製程技術,完成“操作在60 GHz的帶通濾波器”及“互補式金氧半導體與積體電路上方後製程”和“互補式金氧半導體與整合被動元件”之壓控震盪器兩類電路。整合被動元件為低損耗的薄膜製程,利用此製程的高性能優勢,實現一個操作在60 GHz之帶通濾波器,最小介入損耗為1.72 dB (當頻率為57 GHz),在57- 64 GHz的7 GHz頻寬中,介入損耗都小於2.4 dB,且3-dB頻寬有24 GHz (~42%)。第一個壓控振盪器是利用覆晶技術組裝操作在5 GHz互補式金氧半導體與整合被動元件之壓控震盪器,並提出完整“互補式金氧半導體與整合被動元件”協同模擬的設計流程,探討不同整合被動元件-電感擺放的位置(遠離或接近主動元件)對電路特性的影響,實驗結果顯示不論是遠離或接近主動元件相位雜訊都可以達到-120 dBc/Hz(偏移頻率在1 MHz位置),相較於全積體化的金氧半導體壓控震盪器,本論文電路改善了6.7 dBc/Hz的相位雜訊。第二種電路為互補式金氧半導體與積體電路上方後製程之壓控震盪器,操作頻帶在5 GHz,利用高品質因素的積體電路上方電感,使壓控震盪器得到較低相位雜訊,相較於全積體化的金氧半導體製程之壓控震盪器,相位雜訊可改善6.4 dBc/Hz (偏移頻率在1 MHz位置)。此外論文中也探討積體電路上方後製程電感接地的方式對電路之影響,實驗結果顯示接地要遠離矽基板才可獲得高品質的特性。
摘要(英) This dissertation studies the design approaches of system-in-package. Using above-IC post process and integrated passive device (IPD) techniques, we realize a band-pass filter operating at 60GHz and two voltage controlled oscillators (VCOs). One is a CMOS VCO mounted on integrated passive device chip, namely CMOS-IPD VCO, the other is CMOS chip with inductor fabricated by above-IC post process technique, namely CMOS VCO with above-IC inductor. Using the advantage of IPD process, a band-pass filter is implemented and operating over the unlicensed 60-GHz band (57-64 GHz). The experimental results show the minimum insertion loss is 1.72 dB at 57 GHz, the insertion loss is 2.4 dB over the entire 7 GHz pass band, and its 3-dB bandwidth is 24 GHz (~42%). The first CMOS VCO with IPD chip is assembled by flip-chip technology. The design flow of CMOS chip with IPD technology is also proposed to investigate the effects of IPD inductors placed at different location on the top of the CMOS chips. The experimental results show that the VCO can achieve a phase noise of -120 dBc/Hz at 1-MHz offset frequency no matter what place the inductor is located. An improvement of 6.7dB is demonstrated in comparison with a fully integrated CMOS VCO. The second 5GHz CMOS VCO designed and implemented with above-IC inductor demonstrates a measured phase noise of -120 dBc/Hz at 1-MHz offset frequency, 6.4-dB improvement in comparison with a fully integrated CMOS VCO. The grounding issue of inductor on the CMOS and above-IC post process was also carefully examined by the electromagnetic (EM) simulation in this dissertation.
關鍵字(中) ★ 系統封裝
★ 積體電路上方後製程
★ 整合被動元件
★ 互補式金氧半導體
★ 帶通濾波器
★ 壓控震盪器
關鍵字(英) ★ system-in-package
★ above-IC post process
★ integrated passive device
★ CMOS
★ band-pass filter
★ voltage controlled oscillators
論文目次 摘要 i
Abstract ii
誌謝 .. ii
Contents . iv
List of Figure .. vi
List of Tables viii
Chapter 1 Introduction . 1
1.1 Motivation . 1
1.2 Dissertation Contribution .. 2
1.3 Dissertation Overview 3
Chapter 2 Key technologies of System-in-Package . 5
2.1 CMOS Technology .. 6
2.2 Above-IC Post Process Technology 7
2.3 Integrated Passive Device (IPD) . 10
2.4 Bumping Process and Assembly . 13
Chapter 3 V-band Band-pass Filter Design Using Advanced Integrated Passive Devices
Technology 14
3.1 Introduction 14
3.2 Design of Band Pass Filter 15
3.3 EM Simulation and Experimental Results . 18
3.4 Summary . 21
Chapter 4 Voltage Controlled Oscillators Using CMOS and IPD Technologies . 22
4.1 Introduction 22
4.2 Design Flow of CMOS-IPD VCO . 23
4.3 Design of Voltage Controlled Oscillators .. 25
4.4. Experimental Results 28
4.5 Summary . 37
Chapter 5 A 5 GHz Band CMOS VCO Using Above-IC Post Process Technologies .. 38
5.1 Introduction 38
5.2 Characterization of the Above-IC Inductors . 39
5.3 Design of Voltage Controlled Oscillator . 42
5.4 Summary . 46
Chapter 6 Conclusion & Future Work .. 47
6.1 Conclusion . 47
6.2 Future Work .. 48
Reference . 49
Publication List ..54
參考文獻 [1] Rao R. Tummala, “SOP: what is it and why? A new microsystem-integration technology paradigm-Moore’s law for system integration of miniaturized convergent systems of the next decade,” IEEE Trans. Advanced Packaging, vol. 27, no. 2, pp. 241-249, May 2004.
[2] K. Zoschke, M. J. Wolf, M. Topper, O. Ehrmann, T. Fritzsch, K. Kaletta, F. J. Schmuckle, and H. Reichl, “Fabrication of application specific integrated passive devices using wafer level packaging technologies,” IEEE Trans. Advanced Packaging, vol. 30, no. 3, pp. 359-368, Aug. 2007.
[3] P. Pieters, and E. Beyne, “3D wafer level packaging approach towards cost effective low loss high density 3D stacking,” in International Conf. Electronic Packaging Technology, Shanghai, China, Aug. 2006, pp. 1-4.
[4] G. J. Carchon, W. D. Raedt, and E. Beyne, “Wafer-level packaging technology for high-Q on-chip inductors and transmission lines,” IEEE Trans. Microwave Theory and tech., vol. 52, no. 4, pp. 1244–1251, Apr. 2004.
[5] X. Sun, O. Dupuis, D. Linten, G. Carchon, P. Soussan, S. Decoutere, W. D. Raedt, and E. Beyne, “High-Q above-IC inductors using thin-film wafer-level packaging technology demonstrated on 90-nm RF-CMOS 5-GHz VCO and 24-GHz LNA”, IEEE Trans. Advanced Packaging, vol. 29, no. 4, pp. 810–817, Nov. 2006.
[6] Advanced Design System Data Manual, Agilent Technologies Inc., 2009.
[7] S. K. Yong and C. C. Chong, “An overview of multigigabit wireless through millimeter wave technology: Potential and technical challenges,” Wireless Commu.. and Networking, 2007.
[8] Z. Wang, Q. Lai, R.-M. Xu, B. Yan, W. Lin, and Y. Guo, “A millimeter-wave ultra-wideband four-way switch filter module based on novel three-line microstrip structure band-pass filters,” Progress In Electromagnetics Research, Vol. 94, pp. 297-309, 2009.
[9] X. C. Zhang, Z. Y. Yu, and J. Xu, “Novel band-pass substrate integrated waveguide (SIW) filter based on complementary split ring resonators (Csrrs),” Progress In Electromagnetics Research, Vol. 72, pp. 39-46, 2007.
[10] J. Q. Huang and Q. X. Chu, “Compact UWB band-pass filter utilizing modified composite right/left-handed structure with cross coupling,” Progress In Electromagnetics Research, Vol. 107, pp. 179-186, 2010.
[11] M. D. C. Velazquez-Ahumada, J. Martel-Villagr, F. Medina, and F. Mesa, “Design of band-pass filters using stepped impedance resonators with floating conductors,” Progress In Electromagnetics Research, Vol. 105, pp. 31-48, 2010.
[12] C. H. Chen, C. S. Shih, T. S. Horng, and S. M. Wu, “Very miniature dual-band and dual-mode bandpass filter designs on an integrated passive device chip,” Progress In Electromagnetics Research, Vol. 119, pp. 461-476, 2011.
[13] S. M. Wu, C. T. Kuo, and C. H. Chen, “Very compact full differential bandpass filter with transformer integrated using integrated passive device technology,” Progress In Electromagnetics Research, Vol. 113, pp. 251-267, 2011.
[14] J. Brinkhoff and F. Lin, “Integrated filters for 60 GHz systems on CMOS,” in Proc. IEEE Radio-Frequency Integration Technology, pp. 154-157, Dec. 2007.
[15] S. Sun, J. Shi, L. Zhu, S. Rustagi, and K. Mouthaan, “Millimeter-wave bandpass filters by standard 0.18-um CMOS technology,” IEEE Electron Device Lett., vol. 28, no. 3, pp. 220-222, Mar. 2007.
[16] C. Y. Hsu, C. Y. Chen, and H. R. Chuang, “A 60-GHz millimeter-wave bandpass filter using 0.18-um CMOS technology,” IEEE Electron Device Lett., vol. 29, no.3, pp. 246-248, Mar. 2008.
[17] C. Y. Hsu, C. Y. Chen, and H. R. Chuang, “70 GHz folded loop dual-mode bandpass filter fabricated using 0.18um standard CMOS technology,” IEEE Microwave Wireless Component Letter, vol. 18, no. 9, pp. 587-589, Sept. 2008.
[18] B. Yang, E. Skafidas, and R. J. Evans, “Design of 60 GHz millimetre-wave bandpass filters on bulk CMOS,” lET Microwaves, Antennas & Propagation, vol. 3, no. 6, pp. 943-949, 2009.
[19] C. Y. Hsiao, S. S. Hsu., and D. C. Chang, “A compact V-Band bandpass filter in IPD technology,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 10, pp. 531–5334, Oct. 2011.
[20] H. C. Lu, C. S. Yeh, S. A. Wei, and Y. T. Chou,“60 GHz CPW dual-mode rectangular ring bandpass filter using integrated passive devices process,” in Asia Pacific Microwave Conf., Yokohama, Japan, Dec. 2010, pp. 1883–1886.
[21] Y. M. Chen, S. F. Chang, and Y. N. Liao, “A 62 GHz compact low-loss bandpass filter in integrated passive devices technology,” in Asia Pacific Microwave Conf., Melbourne, Australia, Dec. 2011, pp. 1086-1089.
[22] Y. Y. Lim, S. R. Vempati, N. Su, X. Xiao, J. Zhou, A. Kumar, P. P. Thaw, G. Sharma, T. G. Lim, S. Liu, K. Vaidyanathan, and J. H. Lau, “Demonstration of high quality and low loss millimeter wave passives on embedded wafer level packaging platform (EMWLP),” in Electronic Components and Technology Conf., San Diego, U.S., May 2009, pp. 508–515.
[23] J. S. Hong, and M. J. Lancaster, “Couplings of microstrip square open-loop resonators for cross-coupled planar microwave filters,” IEEE Trans. Microwave Theory & Tech., vol. 44, No. 12, pp. 2099–2109, Dec. 1996.
[24] S. Y. Lee and C. M. Tsai, “New cross-coupled filter design using improved hairpin resonators,” IEEE Trans. Microwave Theory & Tech., vol. 48, No. 12, pp. 2482–2490, Dec. 2000.
[25] C. C. Wang, H. A. Yang, Y. C. Shyu, M. H. Li, C. T. Chiu, and S. M. Wu, “Analysis of high performance RF integrated passive circuits using the glass substrate,” in IEEE VLSI Packaging Workshop of Japan, Dec. 2008, pp. 135-138.
[26] L. Liu, S. M. Kuo, J. Abrokwah, M. Ray, D. Maurer, and M. Miller, “Compact harmonic filter design and fabrication using IPD technology,” IEEE Trans. Components and Packaging Technologies, vol. 30, no. 4, pp. 556-562, Dec. 2007.
[27] C. Mo. Nam, and I. H. Jung, “High performance RF integrated circuits using the silicon based RE integrated passive device (RFIPD),” in International Conf. Information, Communications and Signal Processing, Bangkok, Thailand, Dec. 2005, pp. 1357-1361.
[28] K. Liu, and R.C. Frye, “Full-circuit design optimization of a RF silicon integrated passive device,” in IEEE Conf. Electrical Performance of Electronic Packaging, Scottsdale, U.S., Oct. 2006, pp. 327-330,.
[29] K. Stadius, and K. Halonen, “Development of 4-GHz flip-chip VCO module,” in IEEE International Symp. Circuits and Systems, Kobe, Japan, May 2005, pp. 2687-2690.
[30] H. Lee, C. Park, and S Hong, “A quasi-four-pair class-E CMOS RF power amplifier with an integrated passive device transformer,” IEEE Trans. Microwave Theory and tech., vol. 57, no. 4, pp. 752-759, April 2009.
[31] S. P. Liu, C. T. Wang, C. H. Lee, and W. Wang, “Miniaturized WiFi system module using SiP IPD for handheld device applications,” in International Conf. Microsystems, Packaging, Assembly and Circuits Technology, Taipei, Taiwan, Oct. 2007, pp. 146-148.
[32] H. K. Chen, Y. C. Hsu, T. Y. Lin, D. C. Chang, Y. Z. Juang, and S. S. Lu, “CMOS wideband LNA design using integrated passive device,” in IEEE MTT-S int. Microwave Symp., Boston, U.S., June 2009, pp. 673-676.
[33] L. Jia, J. G. Ma; K. S. Yeo; and M. A. Do, “9.3-10.4-GHz-band cross-coupled complementary oscillator with low phase-noise performance,” IEEE Trans. Microwave Theory and tech., vol. 52, no. 4, pp. 1273-1278, April 2004.
[34] A. D. Berny, A. M. Niknejad, and R. G. Meyer, “A 1.8 GHz LC VCO with 1.3 GHz tuning range and digital amplitude calibration,” IEEE Jour. Solid-state Circuits, vol. 40, no. 4, pp. 909-917, April 2005.
[35] A. Kral, F. Behbahani, and A. Abidi, “RF-CMOS oscillators with switched tuning,” in Proc. IEEE Custom Integrated Circuits Conf., Santa Clara, U.S., May 1998, pp. 555-558.
[36] J. W. M. Rogers, J. A. Macedo, and C. Plett, “The effect of varactor nonlinearity on the phase noise of completely integrated VCOs,” IEEE Jour. Solid-state Circuits, vol. 35, no. 9, pp. 1360-1367, Sept. 2000.
[37] C. P. Yue, and S. S. Wong, “On-chip spiral inductors with patterned ground shields for Si-based RF ICs,” IEEE Jour. Solid-state Circuits, vol. 35, no. 5, pp. 743-752, May 1998.
[38] F. Zhang, and P. R. Kinget, “Design of components and circuits underneath integrated inductors,” IEEE Jour. Solid-state Circuits, vol. 41, no. 10, pp. 2265-2271, Oct. 2006.
[39] A. Sutono, D. Heo, Y. J. E. Chen, and J. Laskar, “High-Q LTCC-based passive library for wireless system-on-package (SOP) module development,” IEEE Trans. Microwave Theory and tech., vol. 49, no. 10, pp. 1715–1724, Oct. 2001.
[40] J. L., J. Samitier, C. Cane, P. Losantos, and J. Bausells, “Improvement of the quality factor of RF integrated inductors by layout optimization,” IEEE Trans. Microwave Theory and tech., vol. 48, no. 1, pp. 76–83, Jan. 2000.
指導教授 邱煥凱(Hwann-Kaeo Chiou) 審核日期 2013-8-14
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明