交換電容式類比電路良率提升之設計方法

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羅珮文(Pei-Wen Luo) 查詢紙本館藏

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電機工程學系

論文名稱

交換電容式類比電路良率提升之設計方法
(Design Methodology for Yield Enhancement ofSwitched-Capacitor Analog Integrated Circuits)

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摘要(中)

隨著半導體製程的演進以及元件尺寸愈益縮小，製程變動對電路效能的影響已日趨嚴重。顯而易見，在電路設計上直接影響的就是產品良率降低的問題。為了在設計階段先行觀察元件製程變動的影響，一般設計者會透過蒙地卡羅的統計分析方法，將元件變
動的資訊加入電路模擬中。然而，直接在模擬軟體(如：hspice)中，應用統計的方法描述參數變動做電路分析，是相當的耗費時間，甚至對於大電路而言，這是無法實行的模擬方式。類比電路中除了考量製程變動的影響外，對於實體佈局上的元件匹配問題也相
當重視。最常使用共質心方法來消除元件間不匹配現象。然而，這些規則只能用於佈局時的參考準則，並無一個數學判別式用以判斷實際佈局符合規則的程度，並將其數值化。
鑑於先前技術上不足之處，我們提出了運用元件空間相關性模型的混合電路良率評估器，用以同時模擬元件變動及佈局上匹配問題。可以得知許多混合卅類比電路的效能是直接與電容元件比值息息相關。因此，我們將其技術實際應用在交換電容式的混合類
比電路，並在前段設計流程的系統層級中，分析出電容元件的變動與電路效能的關係，並且評估出高良率的佈局架構。除此之外，我們提出了一啓發式演算法以產生一個高良率的佈局架構。基於我們方法建立在設計流程中的前段層級，除了可以大幅度的降低產
品設計上的成本，更能加速產品上市時間。

摘要(英)

As semiconductor technology continues to shrink, the process variation problems will become inevitable. It is anticipated that the problem of uncontrollable process variation will become more serious. As a result, yield loss caused by process variation is becoming an
important design issue. The key performance of many analog circuits is directly related to accurate capacitor ratios. In general, capacitor mismatches caused by process variation can be classified as two types: random mismatch and systematic mismatch. To analyze process variation in early design stages, process variation information must be input to a circuit simulator, where Monte-Carlo analysis is commonly employed to find out process variation
information and to eliminate the random mismatch in the early stages of design. On the other hand, systematic mismatch is mainly due to asymmetrical layout and processing gradients. The common centroid approach is commonly employed to reduce device mismatches caused
by symmetrical layouts and processing gradients. Among the candidate placements generated by the common centroid approach, however, whichever achieves better matching is generally difficult to be determined without performing the time-consuming yield evaluation process.
This study addresses the impact of capacitor correlation on the yield enhancement of switched-capacitor integrated circuits. The relationships between correlation and mismatch and between correlation and variation of capacitor ratio are also presented. Therefore, both
mismatch and variation of capacitor ratio can be expressed in term of capacitor correlation. Based on a spatial correlation model, this study proposes a design methodology for yield enhancement of analog circuits using switched-capacitor techniques. An efficient and
effective placement generator is developed to derive a placement for a circuit to achieve the highest or near highest correlation coefficient and thus accomplishing a better yield performance. A simple yield analysis is also developed to evaluate the achieved yieldperformance of a derived placement. Results show that the proposed methodology derives a placement which achieves better yield performance than those generated by the common
centroid approach. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed-up the time to market.

關鍵字(中)

★ 類比電路
★ 電容擺置
★ 良率提升

關鍵字(英)

★ Yield Enhancement
★ Switched-Capacitor Analog Integrated Circuits
★ placement

論文目次

Chapter 1 Introduction ................ 1
1.1 Background........................................... 1
1.1.1 Process Variation Definition .....................2
1.1.2 Mismatch Categories...............................3
1.2 Yield Analysis Problem............................... 4
1.3 Capacitor Application and Placement Problem.......... 6
1.3.1 Switched Capacitor Circuit Application ...........6
1.3.2 Capacitor Placement Using Common Centroid
Approach .........................................8
1.4 Impact of Correlation in Yield Analysis..............10
1.5 The Proposed Yield Enhancement Technology........... 15
1.6 Organization........................................ 17
Chapter 2 Yield Enhancement and Correlation
Coefficients.................................. 18
2.1 Spatial Correlation Model........................... 18
2.2 Correlation and Mismatch............................ 20
2.3 Correlation and Variation of Capacitor Ratio ....... 22
2.4 Correlation and Common Centroid .................... 25
2.5 Proposed Methodology Verification....................26
2.5.1 Verify with Mismatch Estimation Methodology .....27
2.5.2 Verify with Measurement Results..................30
Chapter 3 Placement Generator .......................... 33
3.1 Previous Work....................................... 33
3.2 Proposed Heuristic Algorithm........................ 35
3.2.1 Entry Weight Definition..........................36
3.2.2 Entry Assignment.................................37
Chapter 4 Design Methodology for Yield Enhancement...... 45
4.1 Device Parameter Extraction (DPE) .................. 46
4.2 Placement Generator .................................47
4.3 Yield Evaluator .....................................47
4.4. Layout Generator................................... 48
Chapter 5 Experimental Results.......................... 49
5.1 5th-order Cascaded Modulator—General Capacitor
Ratio .............................................. 49
5.2 Third order Sigma-Delta Modulator (SDM)—with
irregular Layout.................................... 54
5.3 Biquad Filter—with Arberitary Capacitors
Ratios ............................................. 58
Chapter 6 Conclusions and Future Works ................. 63
6.1 Summary............................................. 63
6.2 Contributions ...................................... 64
6.3 Future Research Topics ............................. 65
References.............................................. 66

參考文獻

[1] C. Cho, D. Kim, J. Kim, J. -O. Plouchart, and R.
Trzcinski, “Statistical Framework for
Technology-Model-Product Co-Design and Convergence,”
in Proc. of International Conference on Computer-Aided
Design, pp. 503–508, 2007.
[2] M. -F. Lan, A. Tammineedi, and R. Geiger, ”Current
Mirror Layout Strategies for Enhancing Matching
Performance,” Analog Integrated Circuits and Signal
Processing, vol. 28, no. 9, pp. 9-26, Jul. 2001.
[3] J. Liu, S. Dong, X. Hong, Y. Wang, O. He, and S. Goto,
“Symmetry Constraint Based on Mismatch Analysis for
Analog Layout in SOI Technology,” in Proc. of Asia
South Pacific Design Automation Conference, pp. 772-
775, 2007.
[4] H. Masuda, S. Ohkawa, A. Kurokawa and M. Aoki,
“Challenge: Variability Characterization and Modeling
for 65-to 90-nm Processes,” in Proc. of IEEE Custom
Integrated Circuits Conference, pp. 593 – 599, 2005.
[5] R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester,
“Statistical Estimation of Leakage Current Considering
Inter-and Intra-Die Process Variation,” in Proc. of
International Symposiums on Low Power Electronics and
Design, pp. 84-89, 2003.
[6] S. Hausser, S. Majoni, H. Schligtenhorst, and G.
Kolwe, “Systematic Mismatch in Diffusion Resistors
Caused by Photolithography,”IEEE Trans. on
Semiconductor Manufacturing, vol. 16, no. 2, pp. 181-
186, May 2003.
[7] V. Kaushal, “Transistor Matching Introduction,”
Available at http://sites.google.com/site/vlsifaq/my-
top-vlsi-projects/transistor-matching
[8] "Making Matching Measurements for Use in IC Design
Application Note,” Available at
http://cp.literature.agilent.com/litweb/pdf/5988-
5114EN.pdf
[9] H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki,
“Challenge: Variability Characterization and Modeling
for 65- to 90-nm Processes,”, in Proc. of the IEEE
Custom Integrated Circuits Conference, pp. 593
–599, 2005.
[10] A. Maxim and M. Gheorghe, “A Novel Physical Based
Model of Deep-Submicron CMOS Transistors Mismatch for
Monte Carlo SPICE Simulation,” in Proc. of
International. Symposium on Circuits and Systems, pp.
511-514, 2001.
[11] E. Papadopoulou and D. T. Lee, “Critical Area
Computation Via Voronoi Diagrams,”IEEE Trans. on
Computer-Aided Design of Integrated Circuits and
Systems, vol. 18, no. 4, pp. 463-474, April 1999.
[12] E. Papadopoulou, “Critical Area Computation for
Missing Material Defects in VLSI Circuits,” IEEE
Trans. on Computer-Aided Design of Integrated
Circuits and Systems, vol. 20, no. 5, pp. 583-597,
May 2001.
[13] N. Cobb, “Fast Optical and Process Proximity
Correction Algorithms for Integrated Circuit
Manufacturing,” Available at: http://www-
video.eecs.berkeley.edu/papers/ncobb/cobb_phd
_thesis.pdf
[14] D. S. Boning, W. P. Moyne, T. H. Smith, J. Moyne, R.
Telfeyan, A. Hurwitz, S. Shellman, and J. Tayor,
“Run by Run Control of Chemical-Mechanical
Polishing,”IEEE Trans. on Components, Packaging, and
Manufacturing Technology, vol. 19, no.4, pp. 307-314,
October 1996.
[15] D. Johns and K. Marti, Analog Integrated Circuit
Design, Wiley,1997.
[16] A. Boser and B. A. Wooley, “The Design of Sigma-
Delta Modulation Analog-to-Digital Converters,”
IEEE Journal of Solid-State Circuits, vol. 23, no.
6, pp.1298-1308, December 1988.
[17] P. M. Aziz, H. V. Sorensen, and J. V. Spiegel, “An
Overview of Sigma-Delta Converters,” IEEE Signal
Processing Magazine, vol. 68, no. 1, pp. 61–84,
January1996.
[18] L. Yao, “A 1-V 140-μW 88-dB Audio Sigma-Delta
Modulator in 90-nm MOS,” IEEE Journal of Solid-
State Circuits, vol. 39, no. 11, pp. 1809-1818,
November 2004.
[19] O. Choksi and L. R. Carley, “Analysis of Switched-
Capacitor Common Mode Feedback Circuit,” IEEE
Trans. on Circuits Systems II, vol. 50, no. 12, pp.
906–917, December 2003.
[20] M. Ortmanns, F. Gerfers and Y. Manoli, “A Case
Study on a 2-1-1 Cascaded Continuous-Time Sigma-Delta
Modulator,” IEEE Trans. on Circuits and Systems I,
vol. 52, no. 8, pp. 1515-1525, August 2005.
[21] M. J. McNutt, S. LeMarquis, and J. L. Dunkley,
“Systematic Capacitor Matching Errors and Corrective
Layout Procedures,”IEEE Journal of Solid-State
Circuits, vol. 29, no. 5, pp. 611-616, May 1994.
[22] R. Liu, S. Dong, X. Hong, D. Long, and J. Gu, “Two-
Dimensional Common-Centroid Stack Generation
Algorithms for Analog VLSI,” in Proc. of
International Conference on ASIC, pp. 128-131, 2003.
[23] D. Long, X. Hong, and S. Dong, "Optimal Two-Dimension
Common Centroid Layout Automation for MOS Transistor
Unit-Circuit,” in Proc. of Int. Symp. on Circuits and
Systems , pp. 2999-3002, 2005.
[24] D. Sayed and M. Dessouky, ”Automatic Generation of
Common-Centroid Arrays with Arbitrary Capacitor
Ratio,” in Proc. of Design, Automation and Test in
Europe Conference and Exhibition, pp. 576-580, 2002.
[25] Q. Ma, E. F. Y. Young, and K. P. Pun. “Analog
Placement with Common Centroid Constraints,” in
Proc. of International. Conference on Computer-Aided
Design, pp.579-85, 2007.
[26] A. Hastings, The Art of Analog Layout, Prentice Hall,
2000.
[27] J. D. Bruce, H. W. Li, M. J. Dallabetta, and R. J.
Baker. "Analog Layout Using ALAS!,” IEEE Journal of
Solid-State Circuits, vol. 31, no. 2, pp. 271-274,
February 1996.
[28] D. Khalil, M. Dessouky, V. Bourguet, M. M. Louerat,
A. Catheline, and H.Ragai, "Evaluation of Capacitor
Ratios in Automated Accurate Common-Centroid Capacitor
Arrays," in Proc. of International Symposiums on
Quality of Electronic Design, pp.143-147, 2005.
[29] J. S. Doh, D. W. Kim, S. H. Lee, J. B. Lee, Y. K.
Park, M. H. Yoo, and J. T. Kong,” A Unified
Statistical Model for Inter-Die and Intra-Die Process
Variation,” Simulation of Semiconductor Processes
and Devices, 2005.
[30] H. E. Graeb, Analog Design Centering and Sizing,
Springer, 2007.
[31] X. Jinjun, V. Zolotov, and H. Lei, “Robust
Extraction of Spatial Correlation,” IEEE
Trans. on Computer-Aided Design of Integrated
Circuits and Systems, vol. 26, no. 4, pp. 619-631,
April 2007.
[32] P. W. Luo, J. E. Chen, C. L. Wey, L.C. Cheng, J. J.
Chen, and W.C. Wu, ” Impact of Capacitor
Correlation on Yield Enhancement of Mixed-
Signal/Analog Integrated Circuits,” IEEE Trans. on
Computer-Aided Design of Integrated Circuits and
Systems, vol. 27, no. 11, pp. 2097-2101, November
2008.
[33] J. E. Chen, P. W. Luo., and C. L. Wey, “Placement
Optimization for Yield Improvement of Switched-
Capacitor Analog Integrated Circuits,” IEEE Trans. on
Computer-Aided Design of Integrated Circuits and
Systems, vol. 29, no. 2, pp.313-318, February 2010.
[34] P. W. Luo, J. E. Chen, and C. L. Wey, “Design
Methodology for Yield Enhancement of Switched-
Capacitor Analog Integrated Circuits,” Accepted to
appear in IEICE Transactions on Electronics, 2010.
[35] C. S. G. Conroy, W. A. Lane, and M. A. Moran,
“Statistical Design Techniques for D/A Converters,”
IEEE Journal of Solid-State Circuits, vol. 24, no. 4,
pp. 1118-1128, August 1989.
[36] A. Stuart and J. K. Ord, Kendall’s Advanced Theory
of Statistics, Wiley, 1987.
[37] M. Pelgrom, A. Duimnaijer, and A. Welbers, “Matching
Properties of MOS Transistors,” IEEE Journal of
Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440,
October 1989.
[38] X. Dai, C. He, H. Xing, D. Chen, and R. L. Geiger, “
An N-th Order Central Symmetrical Layout Pattern for
Nonlinear Gradient Cancellation”, IEEE International
Symposiums on Circuits and Systems, pp. 4835-4838,
2005.
[39] L. Baldi, B. Franzini, D. Pandini, and R. Zafalon,
“Design Solutions for the Interconnection Parasitic
Effects in Deep Sub-micron Technologies,” Available
at:http://www.sciencedirect.com/
[40] “Semiconductor Manufacturing Course” (EECS
Instructional and Electronics Support).
Available at:
http://california.eecs.berkeley.edu/iesg/
[41] P. W. Luo, J. E. Chen, and C. L. Wey, L.C. Cheng, J.
J. Chen, and W.C. Wu, “IR-Drop Aware Power TSVs
Placement for 3D ICs,” submitted to IEEE/ACM
Design Automation Conference, 2011.

指導教授

魏慶隆、陳竹一
(Chin-Long Wey、Jwu-E Chen)

審核日期

2011-1-11

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