博碩士論文 963209001 詳細資訊




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姓名 闕啟安(Chi-An Chueh)  查詢紙本館藏   畢業系所 材料科學與工程研究所
論文名稱 氫離子佈植對矽鍺/矽異質結構應變釋放之研究及矽鍺奈米線之製作
(Research on Strain-relaxation in Hydrogen-Implanted SiGe/Si Heterostructure and Fabrication of SiGe Nano-Wire Arrays)
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摘要(中) 近年來,鬆弛矽鍺薄膜成長在矽基電子和光電元件上的運用引起關注。因為藉由矽與鍺晶體之晶格常數的調變,與能帶的設計,及其缺陷工程使其有效提昇其上矽通道載子的遷移率,可提供在未來高速電子元件與光電元件之基材所使用。傳統下鬆弛矽鍺緩衝層伴隨厚的膜層及粗糙的表面,這些特性使其厚度增加,成本提昇、並影響之後微影製程和元件運作時加熱的問題。因此新穎的鬆弛矽鍺緩衝層值得研究。本論文利用氫離子佈植製作超薄鬆弛矽鍺薄膜之研究。以矽:硼/矽為基材,成長應變矽鍺薄膜。以劑量為2×1016cm-2之H+離子為佈植之來源,經過快速退火後,以矽:硼/矽為基材之矽鍺薄膜鬆弛程度達78%,此結構之鬆弛程度高過於無埋掩硼層之試片及無離子佈植之試片。透過本論文的研究,利用矽:硼/矽掩埋層與離子佈植可形成超薄且高鬆弛矽鍺薄膜,具有潛力成為在應變矽與III-V光電元件與太陽電池之基材。
此外,隨著尺寸的縮小所造成的量子效應,使得具有奈米結構之矽基材料受到廣大地注目。近幾年來,一維半導體奈米線的基本研究和潛在應用十分熱門。由於其優秀之電子及光電特性可應用在電子元件,光電元件,偵測器,及場發射元件。由於鍺具有不同之能帶架構,矽鍺奈米線和其他矽鍺異質結構對於將來的奈米電子和奈米光電子學應用非常具有潛力。 各種各樣製作一維矽基奈米結構之方法已經發展多時,如蒸氣-液體-固體成長機制。然而此方法一般需要高溫,高真空,及複雜之設備。金屬催化蝕刻法已經被作為一種方法成功發展用建立單晶矽基奈米線。在本研究中,矽鍺奈米線利用金之觸媒作用與聚苯乙烯奈米球微影術,藉由上至下化學蝕刻法在矽鍺虛擬基材上形成。接著利用矽鍺選擇性氧化,來達到提高鍺之濃度已形成高純度鍺之矽鍺奈米線。
摘要(英) Recently, the applications of relaxed SiGe layers in the silicon-based electronics and photonic devices attract many attentions. The high carrier mobility of silicon channel through the adjustable lattice constant, designed energy band and defect engineering can be utilized as the start material for high-speed electronics and photonic devices. The conventional relaxed SiGe buffer layer has thick layer and rough surface. Such a structure resulted in the device with thick thickness and high cost, which suffer deterioration later lithography process and heat-up problem. In this thesis a new buffer with highly relaxed and thin relaxed SiGe layer is proposed. In this thesis, we studied thin relaxed Si1-xGex films by hydrogen ion implantation. A Si0.8Ge0.2 film grown on the substrate consisting of Si:B/Si substrate. H+ ions implant atom with dose of 2×1016 cm-2 was used as the ion source. After RTA treatment, the relaxation (78%) of Si0.8Ge0.2 on Si:B/Si is higher than that without buried boron layer and without ion implantation. By the research in this thesis, thin and relaxed SiGe can be achieved and serves as the potential candidate of starting materials for the strain-Si devices, III-V photonic devices, and solar cells.
In addition, silicon nanostructures have attracted much attention because of their unusual quantum properties and potential applications. One-dimensional semiconductor nanowires have excited much interest recently owing to their importance in fundamental research and potential applications in nanotechnologies. The exhibited unique structural, optical and electronic properties have made them the most promising material systems in areas as diverse as single electron devices, optoelectronics, sensors, and cold cathodes for field-emission displays. With different energy band structure of Germanium, SiGe nanowires and other heterostructures are highly desirable for future nano-electronics and nano-photonics applications. Various methods have been developed to prepare one-dimensional silicon nanostructures, like vapor-liquid-solid (VLS) growth mechanism. However, the growth mechanisms have some limitations as they generally need a high temperature or a high vacuum, templates and complex equipment, or they employ hazardous silicon precursors. Metal catalytic etching has been successfully developed as a method to fabricate silicon nanowires with uniform orientation. In this work, we report the formation of Si0.8Ge0.2 nanowires on Si substrates using Au assisted top-down chemical etching with polystyrene nanosphere lithography (PS NSL). And by the oxidation for SiGe, the composition of germanium in SiGe nanowires is condensed to form the high germanium consistence nanowires.
關鍵字(中) ★ 矽鍺
★ 應變釋放
★ 磊晶
★ 超高真空化學氣相沉積儀
關鍵字(英) ★ UHV/CVD
★ Epitaxy
★ Strain relaxation
★ SiGe
論文目次 Contents
Abstract I
Acknowledgement V
Contents VI
CHAPTER 1 Introduction
1.1 An Overview------------------------------------------1
1.2 Introduction for SiGe Heterostructures---------------3
1.2.1 SiGe Thin Film-------------------------------------4
1.3 Si/SiGe Heterostructure for C-MOSFETs----------------5
1.3.1 SiGe for p-type MOSFET-----------------------------6
1.3.2 Strain Si for n-type MOSFET------------------------7
References-----------------------------------------------9
CHAPTER 2 SiGe Heterostructure
2.1 Material Properties---------------------------------11
2.1.1 Lattice Constants and Lattice Mismatch------------11
2.1.2 Critical Thickness of Si1-xGex on Si--------------13
2.2 Si/Si1-xGex Heterostructures------------------------15
2.2.1 Electronic Properties-----------------------------17
2.2.2 Strain versus Energy Bands------------------------18
2.3 SiGe Virtual Substrates-----------------------------25
2.3.1 Introduction to SiGe Virtual Substrates-----------25
2.3.2 Dislocation and Threading Arms--------------------25
2.4 Fabrication of High-Quality SiGe Thin Film----------29
2.4.1 Relaxed Graded Buffer Technique-------------------29
2.4.2 Compliant Substrates------------------------------30
2.4.3 Low-Temperature Si Buffer Layer-------------------31
2.4.4 Hydrogen Ion Implantation-------------------------32
References----------------------------------------------34
CHAPTER 3 Boron-induced Relaxation in Hydrogen-implanted SiGe/Si(001) Heterostructures
3.1 Motivation------------------------------------------37
3.2 Experimental Procedures-----------------------------38
3.2.1 Transmission Electron Microscope Observation------39
3.2.2 Atomic Force Microscope Observation---------------41
3.2.3 Raman Spectrometer Analysis-----------------------41
3.2.4 High Resolution X-ray Diffraction Analysis--------41
3.2.5 Etch Pit Density Measurements---------------------42
3.3 Results &Discussion---------------------------------42
3.4 Conclusion------------------------------------------61
References----------------------------------------------62
CHAPTER 4 Nanotechnology
4.1 An Overview-----------------------------------------65
4.2 Nanomaterials---------------------------------------69
4.2.1 One-Dimensional Nanomaterials---------------------70
4.2.2 1D Semiconductor and Semiconductor Oxide Nanostructures------------------------------------------70
4.2.3 Silicon Nanowires---------------------------------71
4.2.4 The Characteristics of SiGe-----------------------72
4.3 Self-Assembly---------------------------------------73
4.4 Nanosphere Lithography------------------------------74
4.4.1 Structure of Particle Array-----------------------78
4.5 Self-Assemble Nanosphere Technology-----------------79
4.5.1 Drop Methods--------------------------------------79
4.5.2 Electrostatic Deposition--------------------------79
4.5.3 Dip-Coating---------------------------------------80
4.5.4 Langmuir-Blodgett Coating-------------------------80
4.5.5 Spin-Coating--------------------------------------81
References----------------------------------------------82
CHAPTER 5
Gold Catalysis in the Fabrication of SiGe Nanowires Arrays
5.1 Motivation------------------------------------------87
5.2 Experimental Procedures-----------------------------88
5.2.1 Scanning Electron Microscope Observation----------90
5.3 Results &Discussion---------------------------------91
5.4 Conclusion-----------------------------------------103
References---------------------------------------------104
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指導教授 李勝偉(Sheng-Wei Lee) 審核日期 2009-7-24
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