參考文獻 |
[1] J.-F. Li, R.-S. Tzeng, and C.-W. Wu, “Using syndrome compression for memory builtin self-diagnosis,” in Proc. Int’l Symp. on VLSI Technology, Systems, and Applications (VLSI-TSA), (Hsinchu), pp. 303–306, Apr. 2001.
[2] R.-F. Huang, C.-L. Su, C.-W. Wu, Y.-J. Chang, and W.-C. Wu, “A memory built-in self-diagnosis design with syndrome compression,” in Proc. IEEE Int’l Workshop on Current & Defect Based Testing (DBT), (Napa Valley), pp. 97–102, Apr. 2004.
[3] C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, “A built-in self-test and self-diagnosis scheme for embedded SRAM,” in Proc. Ninth IEEE Asian Test Symp. (ATS), (Taipei), pp. 45–50, Dec. 2000.
[4] J.-F. Li, R.-S. Tzeng, and C.-W. Wu, “Diagnostic data compression techniques for embedded memories with built-in self-test,” Jour. of Electronic Testing: Theory and Applications, vol. 18, pp. 515–527, Aug.-Oct. 2002.
[5] C.-L. Su, R.-F. Huang, C.-W. Wu, Y.-J. Chang, and S.-T. Lin, “Embedded memory diagnostic data compression using differential address,” in Proc. Int’l Symp. on VLSI Technology, Systems, and Applications: Design, Automation and Test (VLSITSA-DAT), (Hsinchu), pp. 20–23, Apr. 2005.
[6] J.-F. Li, “Testing priority address encoder faults in content addressable memories,” in Proc. Int’l Test Conf. (ITC), (Austin), pp. 1–8, Nov 2005, Paper 33.2.
[7] Semiconductor Industry Association, “International Technology Roadmap for Semiconductor (ITRS), 2007 Update,” 2007.
[8] V. N. Yarmolik, S. Hellebrand, and H. Wunderlich, “Self-adjusting output data compression: an efficient BIST technique for RAMs,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), pp. 173–179, 1998.
[9] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, “A programmable BIST core for embedded DRAM,” IEEE Design & Test of Computers, vol. 16, pp. 59–70, Jan.-Mar. 1999.
[10] C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, “BRAINS: a BIST complier for embedded memories,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), (Yamanashi), pp. 299–307, Oct. 2000.
[11] A. Benso, S. Chiusano, G. D. Natale, and P. Prinetto, “An on-line BIST RAM architecture with self-repair capabilities,” IEEE Trans. on Reliability, vol. 51, pp. 123–128, Mar. 2002.
[12] R. Dekker, F. Beenker, and L. Thijssen, “Fault modeling and test algorithm development for static random access memories,” in Proc. Int’l Test Conf. (ITC), pp. 343–352, 1988.
[13] A. J. van de Goor, “Using March tests to test SRAMs,” IEEE Design & Test of Computers, vol. 10, pp. 8–14, Mar. 1993.
[14] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Chichester, England: John Wiley & Sons, 1991.
[15] C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, “A built-in self-test and self-diagnosis scheme for embedded SRAM,” Jour. of Electronic Testing: Theory and Applications, vol. 18, pp. 637–647, Dec. 2002.
[16] J.-C. Yeh, Y.-T. Lai, Y.-Y. Shih, and C.-W. Wu, “Flash memory built-in self-diagnosis with test mode control,” in Proc. IEEE VLSI Test Symp. (VTS), (Palm Springs), pp. 15–20, May 2005.
[17] J.-C. Yeh, K.-L. Cheng, Y.-F. Chou, and C.-W.Wu, “Flash memory testing and built-in self-diagnosis with March-like test algorithms,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, submitted 2005.
[18] J. T. Chen, J. Rajski, J. Khare, O. Kebichi, and W. Maly, “Enabling embedded memory diagnosis via test response compression,” in Proc. IEEE VLSI Test Symp. (VTS), (Marina Del Rey, California), pp. 292–298, Apr. 2001.
[19] J. T. Chen, J. Khare, K. Walker, S. Shaikh, J. Rajski, and W. Maly, “Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring,” in Proc. Int’l Test Conf. (ITC), (Baltmore), pp. 258–267, Oct. 2001.
[20] J.-F. Li and C.-W. Wu, “Memory fault diagnosis by syndrome compression,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), (Munich), pp. 97–101, Mar. 2001.
[21] N. Mukherjee, A. Pogiel, J. Rajski, and J.Tyszer, “High throughput diagnosis via compression of failure data in embedded memory BIST,” in Proc. Int’l Test Conf. (ITC), pp. 1–10, Oct. 2008.
[22] L. Shen and B. F. Cockburn, “An optimal March test for locating faults in DRAMs,”in Proc. IEEE Int’l Workshop on Memory Testing, pp. 61–66, 1993.
[23] V. N. Yarmolik, Y. V. Klimets, A. J. van de Goor, and S. N. Demidenko, “RAM diagnostic tests,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), (San Jose), pp. 100–102, 1996.
[24] T. J. Bergfeld, D. Niggemeyer, and E. M. Rudnick, “Diagnostic testing of embedded memories using BIST,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), (Paris), pp. 305–309, Mar. 2000.
[25] C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, “Error catch and analysis for semiconductor memories using March tests,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), (San Jose), pp. 468–471, Nov. 2000.
[26] R. P. Treuer and V. K. Agarwal, “Built-in self-diagnosis for repairable embedded RAMs,” IEEE Design & Test of Computers, vol. 10, pp. 24–33, June 1993.
[27] S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, and V. N. Yarmolik, “Error detecting refreshment for embedded DRAMs,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 384–390, 1999.
[28] J. Vollrath, U. Lederer, and T. Hladschik, “Compressed bit fail maps for memory fail pattern classification,” in Proc. IEEE European Test Workship (ETW), pp. 125–130, 2000.
[29] D. A. Huffman, “A method for the construction of minimum-redundancy codes,” Proc. IRE, vol. 40, pp. 1098–1101, Sept. 1952.
[30] A. Benso, S. Cataldo, S. Chiusano, P. Prinetto, and Y. Zorian, “HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs,” in Proc. Int’l Test Conf. (ITC), pp. 1038–1045, 1999.
[31] S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, and V. N. Yarmolik, “Efficient online and offline testing of embedded DRAMs,” IEEE Trans. on Computers, vol. 51, pp. 801–809, July 2002.
[32] S. Borri, M. Hage-Hassan, L. Dilillo, P. Girrard, S. Pravossoudovitch, and A. Virazel, “Analysis of dynamic faults in embedded-SRAMs: implications for memory test,” Jour. of Electronic Testing: Theory and Applications, vol. 21, pp. 169–179, Apr. 2005.
[33] W. Needham, C. Prunty, and E. H. Yeoh, “High volume microprocessor test escapes, an analysis of defects our tests are missing,” in Proc. Int’l Test Conf. (ITC), (Washington, DC), pp. 25–34, Oct. 1998.
[34] Z. A.-A. S. Hamdioui and A. van de Goor, “Importance of dynamic faults for new SRAM technologies,” in Proc. IEEE European Test Workshop (ETW), pp. 29–34, 2003.
[35] S. Hamdioui, Z. Al-Ars, and A. J. van de Goor, “Testing static and dynamic faults in random access memories,” in Proc. IEEE VLSI Test Symp. (VTS), (Monterey), pp. 395–400, Apr. 2002.
[36] G. Harutunyan, V. A. Vardanian, and Y. Zorian, “An efficient March-based three-phase fault location and full diagnosis algorithm for realistic two-operation dynamic faults in random access memories,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 95–100, 2000.
[37] G. Harutunyan, V. A. Vardanian, and Y. Zorian, “Minimal March tests for dynamic faults in random access memories,” in Proc. IEEE European Test Symp. (ETS), pp. 43– 48, May 2006.
[38] A. Benso, A. Bosio, S. D. Carlo, G. D. Natale, and P. Prinetto, “March AB, March AB1: new March tests for unlinked dynamic memory faults,” in Proc. Int’l Test Conf. (ITC), pp. 835–841, Nov. 2005.
[39] B. Brown, J. Donaldson, B. Gage, and A. Joffe, “Hardware compression speeds on bitmap fail display,” in Proc. Int’l Test Conf. (ITC), pp. 89–93, 1997.
[40] N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective. Reading, Massachusetts: Addison-Wesley, third ed., 2005.
|