博碩士論文 965201060 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:9 、訪客IP:34.204.0.181
姓名 陳冠宇(Guan-Yu Chen)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 微波毫米波寬頻高效率頻率倍頻器之研製
(Design and Analysis of Microwave and Millimeter-Wave Broadband High-Efficiency Frequency Multipliers)
相關論文
★ 電子式基因序列偵測晶片之原型★ 增強型與空乏型砷化鋁鎵/砷化銦鎵假晶格高電子遷移率電晶體: 元件特性、模型與電路應用
★ 使用覆晶技術之微波與毫米波積體電路★ 注入增強型與電場終止型之絕緣閘雙極性電晶體佈局設計與分析
★ 以標準CMOS製程實現之850 nm矽光檢測器★ 600 V新型溝渠式載子儲存絕緣閘雙極性電晶體之設計
★ 具有低摻雜P型緩衝層與穿透型P+射源結構之600V穿透式絕緣閘雙極性電晶體★ 雙閘極金氧半場效電晶體與電路應用
★ 空乏型功率金屬氧化物半導體場效電晶體 設計、模擬與特性分析★ 離子佈植砷化鎵金屬半導體場效電晶體之研究
★ 碰撞游離係數的量測及其在異質接面雙極性電晶體之設計應用★ 磷化銦鎵/砷化鎵異質接面雙極性電晶體之研製及其集極調變對元件特性的影響
★ 砷化鎵基體異質接面雙極性電晶體之研製與其在積體化功率放大器之應用★ 砷化鋁鎵/砷化鎵異質接面雙極性電晶體之研製及壓控振盪器設計與製程
★ AlGaAs/GaAs PIN/HBT 光檢器/轉阻放大器之積體化光接收器★ 氮化鎵異質結構場效電晶體製作與特性分析
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 本博士論文主要提出應用於高頻本地振盪系統中,微波及毫米波寬頻高效率頻率倍頻器(frequency multiplier)之設計與分析。首先提出兩個利用砷化鎵異質接面雙極性電晶體及高速電子遷移率電晶體製程(GaAs HBT-HEMT process)實現之頻率倍頻器。一個以共閘級/共源級場效電晶體對為基本架構的寬頻高效率頻率二倍頻器(frequency doubler),其輸出3 dB操作頻率可達8至30 GHz。利用共閘級/共源級平衡式架構的反相特性可省略平衡至不平衡轉換器(balun)的使用,進而縮小晶片面積並減少設計複雜度。在8 dBm的輸入功率下,此頻率二倍頻器在頻寬內可達到轉換增益高於-4 dB及基頻抑制能力優於13 dB的能力。量測輸出飽和功率大於10 dBm。此頻率二倍頻器與過往發表寬頻頻率倍頻器相比,可達到一極佳優化指數(FOM),其值為25.14。接著提出一個應用在Ka頻段單晶石砷化鎵異質接面雙極性電晶體及高速電子遷移率電晶體之頻率四倍頻器(frequency quadrupler)。此四倍頻器基本架構為利用兩級修正共基極/共源級平衡式頻率倍頻器串接而成。在此製程下,不同的電晶體組合組態均已對直流偏壓、諧波輸出功率、轉換增益及轉換效率探討並做優化設計。為了減少電晶體輸出相位誤差及更進一步改善基頻抑制能力,兩組相移器(phase shifter)被應用在電路之中。實驗顯示,輸入功率為4 dBm時,此四倍頻器在操作頻率為23至30 GHz之間,轉換增益可優於-1 dB。在28 GHz輸出頻率下,轉換增益最高為2.7 dB,轉換效率及功率附加效率分別大於8及3.6%。最大輸出飽和功率大於8.2 dBm。晶片面積為2x1 mm2。
接著提出一個平衡式砷化鎵異質接面雙極性電晶體及高速電子遷移率電晶體頻率三倍頻器(frequency tripler),3 dB操作頻率為10.2至12.6 GHz。在此電路中,一對共基極/共射極異質接面雙極性電晶體被使用為諧波產生器,以期輸出奇次諧波為反相,偶次諧波為同相。接著利用兩個帶通濾波器來抑制三倍諧波外的其他諧波,增進諧波抑制能力。在輸出使用一個共閘級/共源級主動式平衡至不平衡轉換器將三倍諧波同相相加,提供可能的轉換增益。最後,在輸入端使用一個設計在三倍頻的LC共振器進一步提昇轉換增益。實驗顯示,此三倍頻器的轉換增益為2.8 dB,3 dB頻寬比為21.2%,頻寬內的基頻抑制能力優於47 dB。
最後介紹兩個使用不同轉導提昇(Gm-boosted)技術的頻率二倍頻器。首先提出一個應用在V頻段90奈米互補式金氧半導體製程(90-nm CMOS process)頻率二倍頻器,其使用技術為主動式共源級轉導提昇技術。當轉導提昇技術使用在頻率倍頻器時,因為輸入電壓擺幅等效提昇,可減少輸入驅動功率,因此有效提昇轉換增益。此頻率二倍頻器可達到-3.3 dB的轉換增益,3 dB頻寬比為26.5 %。輸出頻率為60 GHz時,量測輸出飽和功率大於0.8 dBm。接著,利用0.18微米矽鍺雙載子互補式金氧半導體製程(0.18-um SiGe BiCMOS process),成功實現應用在K頻段雙重轉導提昇差動共基極頻率二倍頻器。雙重轉導提昇技術包含主動式共閘級架構和被動式電容交叉耦合(capacitive cross coupling)技術。主動式共閘級轉導提昇級為增益提昇的主要來源,而被動式電容交叉耦合能在不額外增加直流功耗的情況之下,進一步提昇共閘級轉導提昇級本身的增益。詳細的設計流程均在此體現。共源級轉導提昇級及包含交差耦合電容之共閘級轉導提昇級的電流消耗及頻寬也在此做出比較討論。根據提出的雙重轉導提昇架構,此頻率倍頻器可達到-1.3 dB的轉換增益及30.9%的3 dB頻寬比。輸出頻率為26 GHz時,量測輸出飽和功率大於4.5 dBm。
摘要(英) Several microwave and millimeter-wave broadband high-efficiency frequency multipliers are presented in this dissertation for high frequency local oscillation (LO) systems. Two broadband high-efficiency frequency multipliers are designed in heterojunction bipolar transistor and pseudomorphic high electron-mobility transistor (HBT-HEMT) process. First, an 8 to 30 GHz broadband high efficiency, high output power frequency doubler is presented. A common-gate (CG)/common-source (CS) field effect transistor pair is employed in the balanced doubler. The anti-phase property of CG/CS balanced topology can eliminate the need for the additional balun, thus achieving potentially small chip area and reducing design complexity. With an 8-dBm input power, this work features a conversion gain of better than -4 dB with a fundamental rejection of better than 13 dB over the operation bandwidth. The saturation output power (Psat) is higher than 10 dBm. This work presents excellent figure-of-merit (FOM) of 25.14 as compared to other previously reported broadband doublers. A Ka-band monolithic high efficiency frequency quadrupler using a GaAs HBT-HEMT technology is also presented. The frequency quadrupler is constructed cascading two frequency doublers. The frequency doubler employs a modified common-base (CB)/CS topology to enhance the second harmonic efficiently. The dc bias condition, harmonic output power, conversion gain, and efficiency for variable configurations are investigated. Two phase-shifter networks are used to reduce phase error and improve the fundamental suppression. Between 23 and 30 GHz, the proposed frequency quadrupler features a conversion gain of higher than -1 dB with an input power of 4 dBm. The maximum conversion gain is 2.7 dB at 28 GHz with an efficiency of up to 8% and a power-added efficiency (PAE) of 3.6%. The maximum output Psat is higher than 8.2 dBm. The overall chip size is 2x1 mm2.
A 10.2-12.6 GHz high conversion gain high harmonic suppression balanced frequency tripler is implemented in GaAs HBT-HEMT process. A pair of CB/common-emitter (CE) HBTs is used to generate in-phase and out-of-phase harmonics. Two band-pass filters (BPFs) are utilized at inter-stage to enhance the harmonic suppression. A CG/CS HEMTs active balun is employed to combine the third harmonic in-phase and provide conversion gain. Furthermore, a LC resonator designed at the third harmonic frequency is employed at the input to enhance the conversion gain. The proposed frequency tripler shows a conversion gain of 2.8 dB, a fractional bandwidth of 21.2%, and a fundamental suppression of higher than 47 dB.
Two Gm-boosted frequency doublers are presented in chapter 4. First, a V-band 90-nm CMOS frequency doubler using active CS-based Gm-boosted technique is introduced. When the Gm-boosted technique is applied to the frequency multiplier designs, the input driving power reduces due to the boosted input voltage swing. Therefore, the conversion gain can be improved. The proposed frequency doubler exhibits a conversion of -3.3 dB and a fractional bandwidth of 26.5%. At 60-GHz output frequency, the maximum output Psat is higher than 0.8 dBm. A K-band doubly Gm-boosted differential CB frequency doubler using 0.18-um SiGe BiCMOS technology is also presented in this chapter. The doubly Gm-boosted configuration consists of an active CG topology and a passive capacitive cross coupling. The active CG Gm-boosted stage provides gain boosting mainly and the cross-coupled capacitor further boosts the gain of the CG Gm-boosted stage without additional dc power. The design methodology of the frequency doubler using Gm-boosted technique is presented. The comparisons of the current consumption and bandwidth using a CS Gm-boosted stage and a CG Gm-boosted stage with a cross-coupled capacitor are also addressed. Based on the doubly Gm-boosted configuration, the proposed frequency doubler achieves a conversion gain of -1.3 dB and a fractional bandwidth of 30.9%. At 26-GHz output frequency, the maximum output Psat is higher than 4.5 dBm.
關鍵字(中) ★ 倍頻器
★ 寬頻
★ 高效率
★ 平衡式
★ 轉導提昇
★ 砷化鎵
★ 矽鍺雙載子互補式金氧半導體
★ 互補式金氧半導體
關鍵字(英) ★ multiplier
★ broadband
★ high-efficiency
★ balanced
★ Gm-boosted
★ GaAs
★ SiGe BiCMOS
★ CMOS
論文目次 摘要 II
Abstract IV
誌謝 VII
Contents VIII
List of Figures XI
List of Tables XIX
Chapter 1 Introduction 1
1.1 Motivation and Literatures Survey 1
1.2 Dissertation Organization 12
Chapter 2 Broadband High-Efficiency Frequency Multipliers in HBT-HEMT Process 13
2.1 Introduction 13
2.2 MMIC Process and Device Characteristic 15
2.3 An 8-30-GHz Broadband High Efficiency High Output Power Frequency Doubler 18
2.3.1 Circuit Topology and Design 18
2.3.2 Experimental Results and Discussions 26
2.4 A Ka-band High Efficiency Frequency Quadrupler 32
2.4.1 Circuit Design and Analysis 32
2.4.1.1 DC Bias Condition 34
2.4.1.2 Device Selection 36
2.4.1.3 Phase Shifter 38
2.4.2 Circuit Implementation 44
2.4.3 Experimental Results and Discussions 45
2.4.3.1 First-Stage Frequency Doubler 46
2.4.3.2 Second-Stage Frequency Doubler 52
2.4.3.3 Frequency Quadrupler 57
2.4.4 Performance Summary 62
2.5 Summary 66
Chapter 3 A High Gain 10-13-GHz Broadband Balanced Frequency Tripler with High Harmonic Suppression 67
3.1 Introduction 67
3.2 Circuit Topology and Design 68
3.2.1 Harmonic Generator 70
3.2.2 Band-pass Filter 76
3.2.3 Active Balun 77
3.3 Circuit Implementation 82
3.4 Experimental Results and Discussions 83
3.5 Summary 87
Chapter 4 Frequency Doublers using Active Gm-boosted Technique in Si Process 88
4.1 Introduction 88
4.2 Gm-boosted Technique 90
4.3 A V-band 90-nm CMOS Frequency Doubler using Active CS-based Gm-boosted Technique 93
4.3.1 Circuit Topology and MMIC Process 93
4.3.2 Frequency Doubler Core 95
4.3.3 Gm-Boosted Stage 96
4.3.4 Circuit Implementation 99
4.3.5 Experimental Results and Discussions 100
4.3.6 Performance Summary 108
4.4 A K-band SiGe BiCMOS Frequency Doubler using Doubly Gm-boosted Technique 109
4.4.1 Circuit Topology and MMIC Process 109
4.4.2 Frequency Doubler Core 111
4.4.3 Gm-Boosted Stage 113
4.4.4 Cross-coupled Capacitor 122
4.4.5 Circuit Implementation 123
4.4.6 Experimental Results and Discussions 124
4.4.7 Performance Summary 129
4.5 Summary 131
Chapter 5 Conclusions and Future Works 132
Appendix A The Voltage Gain of The CB HBT and CS HEMT with The Phase Shifters 135
Appendix B The Voltage Gain of The CE HBT with The Phase Shifters 138
Appendix C The Input Admittance of The CB Frequency Doubler with The CS Gm-boosted Stage 140
Appendix D The Input Admittance of The Differential CB Frequency Doubler with The CG Gm-boosted Stage Combined with a Cross-coupled Capacitor 142
Reference 144
Publication list 149
參考文獻 [1] C. Karnfelt, R. Kozhuharov, H. Zirath, and I. Angelov, “High-purity 60 GHz-band single-chip X8 multipliers in pHEMT and mHEMT technology,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 6, pp. 2887–2897, Jun. 2006.
[2] K. Yuk and G. R. Branner, “Advances in active microwave frequency multipliers,” in IEEE Int. Midwest Symp. on Circuits and Systems, Aug. 2011, pp. 1–4.
[3] S. Ko, J. Kim, T. Song, E. Yoon, and S. Hong, “K- and Q-bands CMOS frequency sources with X-band quadrature VCO,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 9, pp. 2798–2800, Sep. 2005.
[4] C.-Y. Yang, C.-H. Chang, J.-M. Lin, and H.-Y. Chang, “A 20/40-GHz dual-band voltage-controlled frequency source in 0.13-m CMOS,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 8, pp. 2008–2016, Aug. 2011.
[5] K.-Y. Lin, J.-Y. Huang, J.-L. Kuo, C.-S. Lin, and H. Wang, “A 14–23 GHz CMOS MMIC distributed doubler with a 22-dB fundamental rejection,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2008, pp. 1477–1480.
[6] F. Ellinger and H. Jackel, “Ultracompact SOI CMOS frequency doublerfor low power applications at 26.5–28.5 GHz,” IEEE Microw. Wireless Compon. Lett., vol. 14, no. 2, pp. 53–55, Feb. 2004.
[7] H. Zirath, T. Masuda, R. Kozhuharov, and M. Ferndahl, “Development of 60 GHz front-end circuits for a high-data-rate communication system,” IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1640–1649, Oct. 2004.
[8] Y. Liu, T. Yang, Z. Yang and J. Chen, “A 3–50 GHz ultra-wideband pHEMT MMIC balanced frequency doubler ,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 9, pp. 629–631, Sept. 2008.
[9] S. Mahon, P. Beasly, J. Harvey and A. Bessemoulin, “A broadband millimetre-wave differential pHEMT frequency doubler MMIC,” in Proc. IEEE CSIC’05, Nov. 2005, pp. 212–215.
[10] K.-L. Deng, and H. Wang, “A miniature broad-band pHEMT MMIC balanced distributed doubler,” IEEE Trans. Microw. Theory Tech., vol. 51, pp. 1257-1261, Apr. 2003.
[11] H.-P. Forstner; F. Starzer, G. Haider, C. Wagner, M. Jahn, “Frequency quadruplers for a 77GHz subharmonically pumped automotive radar transceiver in SiGe,” in 2009 Eur. Microw. Integrated Circuits Conf., (EuMIC), Sept. 28–29, 2009, pp. 188–191.
[12] Juo-Jung Hung, Timothy M. Hancock, and Gabriel M. Rebeiz, “A high-efficiency miniaturized SiGe Ku-band balanced frequency doubler,” in IEEE RFIC Symp. Dig., Jun. 2004, pp. 219-222.
[13] C.-C. Weng, Z.-M. Tsai, and H. Wang, “A K-band miniature, broadband, high output power HBT MMIC balanced doubler with integrated balun,” in IEEE Eur. Microw. Conf. Dig., Oct. 4–6, 2005, vol. 3, pp. 1–3.
[14] D.-W. Kang, D.-H. Baek, S.-H. Jeon, J.-W. Park, and S. Hong, “A miniaturized K-band balanced frequency doubler using InGaP HBT technology,” IEEE MTT-S Symp. Dig., Jun. 2003, vol. 1, 8-13, pp. 107-110.
[15] S. Hackl and J. Böck, “42 GHz active frequency doubler in SiGe bipolar technology,” in Proc. Int. Conf. Microw. Technol., Aug. 2002, pp. 54–47.
[16] K.-Y. Lin, J.-Y. Huang, C.-K. Hsieh and S.-C. Shin, “A broadband balanced distributed frequency doubler with a sharing collector line,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 2, pp. 110–112, Feb. 2009.
[17] B.-J. Huang, Z.-M. Tsai, B.-J. Huang, K.-Y. Lin, H. Wang and C.-C. Chiong, “A GaAs-based HBT 31-GHz frequency doubler with an on-chip voltage,” in 2008 Asia Pacific Microw. Conf. Dig., Dec. 2008, pp.1-4.
[18] J. Li, Y.-Z. Xiong, W.-L. Goh, and W. Wu, “A 27–41 GHz frequency doubler with conversion gain of 12 dB and PAE of 16.9%,” IEEE Microw. Wireless Compon. Lett., vol. 22, no. 8, pp. 427- 429, Aug. 2012.
[19] J. Zhang, M. Bao, D. Kuylenstierna, S. Lai, and H. Zirath, “Broadband Gm-boosted differential HBT doublers with transformer balun,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 11, pp. 2953-2960, Nov. 2011.
[20] T. Hiraoka, T. Tokumitsu, and M. Akaike, “A miniaturized broadband MMIC frequency doubler,” IEEE Trans. Microw. Theory Tech., vol. 38, pp. 1932-1936, Dec. 1990.
[21] H.-Y. Chang, G.-Y. Chen, and Y.-M. Hsin, “A broadband high efficiency high output power frequency doubler,” IEEE Microw. Wireless Compo Lett., vol. 20, no. 4, pp. 226-228, Apr. 2010.
[22] S.-H. Weng, G.-Y. Chen, H.-Y. Chang, and Y.-M. Hsin, “A K-band high efficiency high output power CG-CS frequency doubler in 0.5-µm GaAs E/D-mode PHEMT process,” in 2011 Asia Pacific Microw. Conf. Dig., Dec. 2011, pp.1258-1261.
[23] G.-Y. Chen, Y.-L. Yeh, H.-Y. Chang, and Y.-M. Hsin, “A Ka-band broadband active frequency doubler using CB-CE balanced configuration in 0.18 µm SiGe BiCMOS process,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012, pp.1-3.
[24] K. Shirakawa, Y. Kawasaki, Y. Ohashi, and N. Okubo, “A 15/60 GHz one-stage MMIC frequency quadrupler,” in IEEE Microw. Millimeter-Wave Monolithic Circuits Symp. Dig., Jun. 1996, pp. 35–38.
[25] C. Wang, and V. Fusco, “High-purity 56–66GHz quadrupler for V-band radio homodyne and heterodyne transceiver applications,” in Int. SOC Conf., Sept. 9–11, 2009, pp. 203–205.
[26] Y. Campos-Roca, L. Verweyen, M. Femdindez-Barciela, M. C. Curris-Francos, E. Sdnchez, A. HUlsmann, and M. Schlechtweg, “Millimeter-wave active MMIC frequency multipliers,” in Eur. Microw. Conf., Sept. 24–26, 2001, pp. 1–4.
[27] N.-C. Kuo, Z.-M. Tsai, K. Schmalz, J. C. Scheytt, and H. Wang, “A 52–75 GHz frequency quadrupler in 0.25-µm SiGe BiCMOS process,” in Eur. Microw. Integrated Circuits Conf., 2010 (EuMIC), Sept. 27–28, 2010, pp. 365–368.
[28] P. Sandhiya , J. G.E Mayock, and C. Buck, “A Ka band, low power dissipation, high spectral purity GaAs pHEMT MMIC X4 multiplier,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2006, pp. 1513–1516.
[29] Y. Yamaguchi, T. Kaho, and K. Uehara., “A highly integrated X-band frequency quadrupler MMIC using 3D-MMIC technology,” in 2007 IEEE RFIC Symp. Dig., Jun. 2007, pp.757-760.
[30] A. Boudiaf, D. Bachelet, and C. Rumelhard, “38 GHz MMIC PHEMT-based tripler with low phase-noise properties,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2000, pp. 509-512.
[31] H. Fudem and E.C. Niehenke, “Novel millimeter wave active MMIC triplers,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 1998, pp. 387-390.
[32] J.-C. Chiu, C.-P. Chang, M-P Houng, and Y.-H. Wang, “A 12-36 GHz PHEMT MMIC balanced frequency tripler,” IEEE Microw. Wireless Compo Lett., vol. 16, no. 1, pp. 19-21, Jan. 2006.
[33] S.-W. Lin, H.-C. Chiu, and J.S. Fu, “High-efficiency Ka band microwave monolithic integrated circuit frequency tripler using lumped-element balun,” IET Microw. Antennas Propag., vol. 5, no.1, pp. 30-37, Jan. 2011.
[34] V. Puyal , A. Konczykowska , P. Nouet , S. Bernard , S. Blayac , F. Jorge , M. Riet, and J. Godin “DC-100 GHz frequency doublers in InP DHBT technology,” IEEE Trans. Microw. Theory Tech., vol. 53, pp. 1388, Apr. 2005.
[35] G.-Y. Chen, H.-Y. Chang, S.-H. Weng, C.-C. Shen, Y.-L. Yeh, J.-S. Fu, Y.-M. Hsin, and Y.-C. Wang, “Design and analysis of a Ka-band monolithic high-efficiency frequency quadrupler using GaAs HBT–HEMT common-base/common-source balanced topology,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 10, pp. 3674–3689, Oct. 2013.
[36] K.-Y. Lin, J.-Y. Huang, and S.-C. Shin, “A K-band CMOS distributed doubler with current-reuse technique,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 5, pp. 308–310, May 2009.
[37] P.-H. Tsai, Y.-H. Lin, J.-L. Kuo, Z.-M. Tsai, and H. Wang, “Broadband balanced frequency doublers with fundamental rejection enhancement using a novel compensated marchand balun,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 5, pp. 1913-1923, May 2013.
[38] J.-H. Chen and H. Wang, “A high gain, high power K-band frequency doubler in 0.18 m CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 9, pp. 522–524, Sep. 2010.
[39] J. T. Sun, Q. Liu, Y. J. Suh, T. Shibata, and T. Yoshimasu, “A 22-30 GHz balanced SiGe BiCMOS frequency doubler with 47dBc suppression and low input drive power,” in Asia-Pacific Microw. Conf. Dig., Dec. 2009, pp. 2260-2263.
[40] A. Y.-K. Chen, Y. Baeyens, Y.-K. Chen, and J. Lin, “A 36–80 GHz high gain millimeter-wave double-balanced active frequency doubler in SiGe BiCMOS,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 9, pp. 572–574, Sep. 2009.
[41] J.-J. Hung, T. M. Hancock, and G. M. Rebeiz, “High-power high-efficiency SiGe Ku- and Ka-band balanced frequency doublers,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 754–761, Feb. 2005.
[42] D. Y. Jung, and C. S. Park, “A low-power, high-suppression V-band frequency doubler in 0.13 m CMOS,” IEEE Microw. Wireless Common. Lett., vol. 18, no. 8, pp. 551-553, Aug. 2008.
[43] J. Chen, P. Yan, W. Hong, “A 50-70 GHz frequency doubler in 90 nm CMOS,” in Microwave Workshop Series on Millimeter Wave Wireless Technology and Applications (IMWS), 2012 IEEE MTT-S International, Sept. 2012, pp. 1-3, 18-20,.
[44] M. Ferndahl, B. M. Motlagh, and H. Zirath, “40 and 60 GHz frequency doublers in 90-nm CMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2004, pp. 179-182.
[45] M. Kantanen, J. Holmberg, T. Karttaavi, and J. Volotinen, “60 GHz frequency conversion 90 nm CMOS circuits,” in Proc. 3rd Eur. Microw. Integr. Circuits Conf., Oct. 2008, pp. 60-63.
[46] T. Cho, E. Dukatz, M. Mack, D. MacNally, M. Marringa, S. Mehta, C. Nilson, L. Plouvier, and S. Rabii, “A single-chip CMOS direct-conversion transceiver for 900 MHz spread-spectrum digital cordless phones,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 1999, pp. 228–229.
[47] W. Zhou, X. Li, S. Shekhar, S. H. K. Embabi, J. P. de Gyvez, D. J. Allstot, and E. Sanchez-Sinencio, “A capacitor cross-coupled common-gate low-noise amplifier,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 12, pp. 875–879, Dec. 2005.
[48] X. Li, S. Shekhar, and D. J. Allstot, “Gm-boosted common-gate LNA and differential Colpitts VCO/QVCO in 0.18-m CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2609–2619, Dec. 2005.
[49] X. Fan, H. Zhang, and E. Sánchez-Sinencio, “A noise reduction and linearity improvement technique for a differential cascode LNA,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 588–599, Mar. 2008.
[50] I. R. Chamas and S. Raman, “Analysis, design, and X-band implementation of a self-biased active feedback Gm-boosted common-gate CMOS LNA,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 3, pp. 542–551, Mar. 2009.
[51] F. Belmas, F. Hameau, and J. Fournier, “A low power inductorless LNA with double Gm enhancement in 130 nm CMOS,” IEEE J. Solid-State Circuits, vol.47, no.5, pp. 1094-1103, May 2012.
[52] J. Zhang, M. Bao, D. Kuylenstierna, S. Lai, and H. Zirath, “Transformer-based broadband high-linearity HBT Gm-boosted transconductance mixers,” IEEE Trans. Microw. Theory Tech., vol. 62, no. 1, pp. 92–99, Jan. 2014.
[53] H. Wang, R. Lai, L. Tran, J. Cowles, Y. C. Chen, E. W. Lin, H. H. Liao, M. K. Ke, T. Block, and H. C. Yen, “A single-chip 94 GHz frequency source using InP-based HEMT–HBT integration technology,” in IEEE RFIC Symp. Dig., Jun. 1998, pp. 275–278.
[54] K. W. Kobayashi, A. K. Oki, D. K. Umemoto, T. R. Block, and D. C. Streit, “A novel self-oscillating HEMT–HBT cascode VCO-mixer using an active tunable inductor,” IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 870–876, Jun. 1998.
[55] H.-Y. Chang, Y.-C. Liu, S.-H. Weng, C.-H. Lin, Y.-L. Yeh, and Y.-C. Wang, “Design and analysis of a DC–43.5-GHz fully integrated distributed amplifier using GaAs HEMT–HBT cascode gain stage,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 2, pp. 443-455, Feb. 2011.
[56] C.-C. Shen, H.-Y. Chang, and Y.-C. Wang, “A Monolithic 3.5-to-6.5 GHz GaAs HBT-HEMT/common-emitter and common-gate stacked power amplifier,” IEEE Microw. Wireless Compon. Lett., vol. 22, no. 9, pp. 474–476, Sept. 2012.
[57] S.-H. Weng, H.-Y. Chang, C.-C. Chiong, and Y.-C. Wang, “Gain-bandwidth analysis of broadband darlington amplifiers in HBT-HEMT process,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 11, pp. 3458-34735, Nov. 2012.
[58] “Sonnet® User’s Guide,” 12th ed. Sonnet Software Inc., North Syracuse, NY, 2009.
[59] E. Camargo, Design of FET Frequency Multipliers and Harmonic Oscillators, Artech House, 1998.
[60] S. A. Maas, Nonlinear Microwave and RF Circuits, Artech House, 2003.
[61] S. Bousnina, P. Mandeville, A. B. Kouki, R. Surridge, and F. M. Ghannouchi, “Direct parameter-extraction method for HBT small-signal mode,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 2, pp. 529–536, Feb. 2002.
[62] G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, “A new method for determining the FET small-signal equivalent circuit,” IEEE Trans. Microw. Theory Tech., vol. 36, no. 7, pp. 1151–1159, Jul. 1988.
[63] Y.-L. Yeh, and H.-Y. Chang, “A W-band wide locking range and low DC power injection-locked frequency tripler using transformer coupled technique,” IEEE Trans. Microw. Theory Tech., vol.61, no.2, pp.860-870, Feb. 2013.
指導教授 辛裕明、張鴻埜(Yue-Ming Hsin Hong-Yeh Chang) 審核日期 2014-8-20
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明