24 GHz汽車防撞雷達收發積體電路之研製

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姓名

吳翊碩(Yi-shuo Wu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

24 GHz汽車防撞雷達收發積體電路之研製
(Design of 24 GHz Radar Integrated Circuits for Automotive Applications)

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摘要(中)

本論文主要是設計並實現一24 GHz 汽車防撞雷達收發積體電路，此收發積體電路中各個子電路的設計與製作皆是採用穩懋半導體所提供的0.5 ?m E/D-PHEMT製程。
首先本論文的第一章緒論中會介紹汽車雷達測距與測速的原理，第二章則是壓控振盪器的設計原理，第三章為應用於K頻段的差動壓控振盪器，輸出頻率變化可從18.8到27.5 GHz，擁有可調頻率的百分比為38%，輸出功率皆大於4 dBm以上，其性能指標(FOMP)可達-177 dBc/Hz，另外，一個自我定義可變電容大訊號模型亦被提出。第四章與第五章分別為24 GHz 汽車防撞雷達發射與接收系統，第四章的發射系統電路架構是由第三章的差動壓控振盪器和兩級串接功率放大器所組成，操作的頻率為21.7到26 GHz，輸出功率皆大於13 dBm。第五章的接收系統電路架構包含第三章的差動壓控振盪器、低雜訊放大器、緩衝放大器及混頻器，射頻端操作頻率涵蓋22到26 GHz，射頻端至中頻端的轉換增益皆在9 dB以上，降頻後的中頻操作頻率為0.1到3.4 GHz。第六章則是利用台積電的0.18 ?m互補式金氧半場效電晶體製程來設計頻率合成器，且在閉迴路狀態下量測到頻率合成器輸出頻率鎖定1.472 GHz的結果。第七章為結論。

摘要(英)

The goal of the thesis is to design and implement a 24-GHz radar integrated circuits for the automotive radar applications. The radar integrated circuits have been designed and fabricated using WIN Semiconductors 0.5-?m E/D-PHEMT technology.
First, the introduction and the theory of the oscillation are presented in chapter 1 and chapter 2, respectively. In chapter 3, a differential voltage controlled oscillation circuit is presented for K-band applications. The frequency of the differential VCO is from 18.8 to 27.5 GHz with a tuning bandwidth of 38% and an output power of higher than 4 dBm. The differential VCO demonstrates a figure-of-merit of -177 dBc/Hz. Besides, a user-defined varactor model has been presented in this chapter. The radar receiver and transmitter for the automotive radar applications are presented in chapter 4 and chapter 5, respectively. The radar transmitter consistes of a differential VCO and a two-stage power amplifier. The frequency of the radar transmitter is from 21.7 to 26 GHz with an output power of higher than 13 dBm. The radar receiver consistes of a differential VCO, a low noise amplifier, a buffer amplifier and a mixer. The RF frequency of the radar receiver is from 21.7 to 26 GHz with a conversion gain of higher than 9 dB and an IF frequency of from 0.1 to 3.4 GHz. The frequency synthesizer are presented using TSMC 0.18-?m CMOS peocess in chapter 6. The measured output frequency is locked at 1.472 GHz in close loop condition. Finally, the conclusion is given in chapter 7.

關鍵字(中)

★ 頻率合成器
★ 壓控振盪器
★ 收發機

關鍵字(英)

★ PLL
★ Transceiver
★ VCO

論文目次

摘要 I
ABSTRACT II
目錄 III
圖目錄 V
表目錄 IX
第一章緒論 1
1.1 研究動機 1
1.2 相關研究發展 2
1.3 雷達原理簡介 3
1.4 論文架構 7
第二章壓控振盪器設計原理 8
2.1 壓控振盪器簡介 8
2.2 振盪器電路設計方法 8
2.2.1 回授法 9
2.2.2 負電阻法 10
2.2.3 振盪器模型 17
2.3 壓控振盪器電路相關設計參數 19
2.3.1 相位雜訊 19
2.3.2 調諧範圍 21
2.3.3 負載拉移 21
2.3.4 諧波抑制量 22
2.3.5 功率消耗 22
2.4 基本振盪器電路架構 22
2.4.1 交互耦合振盪器 22
2.4.2 考畢茲振盪器 26
第三章利用假晶格高電子遷移率電晶體設計K頻段差動壓控振盪器 30
3.1 簡介 30
3.2 K頻段差動壓控振盪器設計與分析 31
3.3 K頻段壓控振盪器模擬與量測結果 42
3.4 可變電容模型的建立 46
3.4.1 元件參數萃取流程介紹 46
3.4.2 外部參數萃取 47
3.4.3 內部參數萃取 56
3.4.4 可變電容模型建立結果 59
3.5 結果與討論 63
第四章 24 GHZ汽車防撞發射系統 66
4.1 簡介 66
4.2功率放大器簡介 66
4.3 K頻段兩級串接功率放大器設計 69
4.4 K頻段兩級串接功率放大器模擬與量測結果 71
4.5 24 GHZ汽車防撞發射系統模擬與量測結果 76
4.5 總結 80
第五章 24 GHZ汽車防撞接收系統 82
5.1 簡介 82
5.2 K頻段低雜訊放大器模擬與量測結果 82
5.3 K頻段緩衝放大器模擬與量測結果 89
5.4 K頻段單平衡混頻器模擬與量測結果 95
5.5 K頻段差動壓控振盪器和緩衝放大器之整合電路模擬與量測結果 104
5.6 24 GHZ汽車防撞接收系統模擬與量測結果 108
5.7 總結 115
第六章互補式金氧半場效電晶體之頻率合成器設計 116
6.1 簡介 116
6.2 頻率合成器的原理與設計 117
6.2.1 相位頻率檢測器、充電泵及低通濾波器原理與設計 117
6.2.2 預除器及可程式化計數器原理與設計 122
6.3 頻率合成器的量測結果 124
6.3.1 壓控振盪器量測結果 124
6.3.2 預除器及可程式化計數器量測結果 124
6.3.3 頻率合成器量測結果 129
6.4 總結 131
第七章結論 132
參考文獻 135

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指導教授

張鴻埜(Hong-Yeh Chang)

審核日期

2009-7-22

推文