混合式加法器設計

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姓名

張劭鍇(Shao-kai Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

混合式加法器設計
(Hybrid Adder Designs)

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摘要(中)

本論文提出一個快速的六十四位元加法器﹐使用動態的邏輯電路及傳輸閘的架構﹐應用於Brent-Kung Tree。此加法器為混合式的加法器架構，其採用前瞻進位單元和多工器且具有8個邏輯閘階層。由模擬結果顯示，混合加法器在最壞情況的延遲為298ps，而使用的製程技術為TSMC 0.18 um 2P6M CMOS technology，電源電壓為1.8伏特。同時我們也在其他的先進製程中模擬，模擬結果顯示，混合加法器在最壞情況的延遲為110ps，而使用的製程技術為UMC 90 nm 1P9M CMOS Low-K technology，電源電壓為1伏特。

摘要(英)

The thesis presents a fast 64-bit adder based on domino logics and pass transmission gates in the Brent-Kung Tree. The proposed adder uses a hybrid adder of Carry Look-Ahead and MUX architecture in 8 logic levels. Simulation results show that the proposed hybrid adder achieves a delay of 298ps, where the TSMC 0.18 um 2P6M CMOS technology with the supply voltage of 1.8V. Based on UMC 90 nm 1P9M CMOS Low-K technology with the supply voltage of 1V, the proposed 64-bit hybrid adder achieves a delay of 110ps with 6mW power dissipation.

關鍵字(中)

★ 混合式加法器
★ 前瞻進位加法器
★ 跳躍進位加法器
★ 平行預算加法器

關鍵字(英)

★ Parallel Prefix adder
★ Carry Skip Adder
★ Carry lookahead adder
★ Hybrid Adder

論文目次

摘要 i
Abstract ii
致謝 iii
圖目錄 vi
表目錄 viii
一、前言 1
1.1研究動機 1
1.2論文大綱 1
二、預備知識 2
2.1 Carry Look-Ahead Addition 2
2.2 Ling’s Adder 4
2.3 Parallel-Prefix (P-P) Addition 5
2.3.1 Kogge-Stone Tree 5
2.3.2 Brent-Kung Tree 6
2.3.3 Han-Carson 6
2.3.4 Sklansky 7
2.3.5 總結 7
2.4 Fan-out of 4 8
三、我們提出的加法器架構 10
3.1 回顧以前的加法器 10
3.2 新加法器的架構 10
3.2.1 Hybrid Adder Unit 12
3.2.2應用於六十四位元加法器 14
3.2.3進位的方式 16
3.2.4 新架構和可組態加法器 17
3.3 總結新架構的優點 21
四、電路設計 23
4.1 Domino Logics 23
4.2 Transmission Gates (MUX) 24
4.3 Critical Path and Driving Power 27
4.4 Floorplaning 30
五、模擬分析以比較 33
5.1模擬分析 33
5.2 Layout 33
5.3 比較 39
六、結論與未來工作 42
6.1結論 42
6.2未來工作 42
參考文獻 43

參考文獻

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[14] D. Stasiak, F. Mounes-Toussi, S.N. Storino, "A 440-ps 64-bit Adder in 1.5-V 0.18 μm Partially Depleted SOI Technology," IEEE Journal of Solid-State Circuits(JSSC), vol. 33, no. 10, pp. 1546-1552, October 2001.
[15] J. Park, H. Ngo, J. Silberman, S. Dhong, "470-ps 64-bit Parallel Binary Adder," Symposium on VLSI Circuits Digest of Technical Papers, pp. 192-193, June 2000.
[16] S. Lee, R. Woo, H. Yoo, "480 ps 64-bit Race Logic Adder," Symposium on VLSI Circuits Digest of Technical Papers, pp. 27-28, June 2001.
[17] A. Neve, H. Schettler, T. Ludwig, D. Flandre, "Power Delay Product Minimization in High-Performance 64-bit Carry-Select Adders," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 12, on. 3, pp. 235-244, March 2004.
[18] J. Kim, R. Joshi, C. Chuang, K. Roy, "SOI-Optimized 64-bit High-Speed CMOS Adder Design," Symposium on VLSI Circuits Digest of Technical Papers, pp. 122-125, June 2002.

指導教授

魏慶隆、謝韶徽
(Chin-Long Wey、Shao-Hui Shieh)

審核日期

2010-11-18

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