一個固態硬碟的多處理器架構與分散式控制演算法

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姓名

王志均(Chih-chun Wang) 查詢紙本館藏

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資訊工程學系

論文名稱

一個固態硬碟的多處理器架構與分散式控制演算法
(A Multi-core Based Architecture and Distributed Control Algorithm for Solid State Disk Controller)

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摘要(中)

目前現存之固態硬碟控制器均以單處理器架構為主，並以處理器作為固態硬碟中快閃記憶體管理之核心，此一核心必須執行一個FTL中介軟體(middleware)。由於固態硬碟控制演算法複雜性及整體容量愈趨升高，控制器之效能需求也越來越重要。本論文提出一個多核心固態硬諜控制器架構，搭配一個分散式控制演算法。此架構能夠將FTL的執行分散於各處理器上進而將所需耗費之時間盡可能的隱藏於背景中，因此可大幅提升控制器性能。
為了驗證此架構之效能，本研究實作了一個模擬器，透過搜集實際使用者於Windows XP之存取紀錄並將其輸入於模擬器中執行，可證明雙處理器之控制器可縮短整體存取時間達32%，而4處理器之架構可縮短處理器時間達60%。
最後我們實作了一個FPGA-based系統晶片雛型(prototype)，透過實驗可證明與單處理器之控制器相比，雙處理器之控制器可增進效能1.6倍以上，而4處理器則可增進效能達2.7倍以上。

摘要(英)

Most existing architectures of SSD(solid-state disk) controller are single processor to proceed the flash translation layer (FTL) algorithm. However, because of the complexity of system’s functionalities and capacities of flash memory are continuously increased, the design of SSD controller become more delicate than before. In this paper, we propose a multi-core SSD controller architecture. Under this architecture, the latency of processor executing the FTL operations in the background can be mostly eliminated.
To verify the proposed architecture, we implement a simulator and collect the hard drive activity on Windows XP platform. By the experimental results of simulation, we can demonstrate that even with the dual processor based architecture, the system’s access time can be shortened about 32% compared to the single processor based one under usual hard drive accessing convention, and further, the access time can be shortened more than 60% on the system with four processors.
After that, we implement a multi-core based SSD controller prototype on FPGA. By the experimental result on the real system, we can demonstrate that dual processor based controller can improve the system’s performance about 160%, and the controller with four processors can improve the system’s performance about 270%.

關鍵字(中)

★ 多處理器
★ 固態硬諜

關鍵字(英)

★ solid state disk
★ MPSOC

論文目次

摘要 IV
ABSTRACT V
誌謝 VI
目錄 VII
圖目錄 IX
表目錄 XI
第一章、緒論 1
1-1 研究動機 3
1-2相關文獻探討 4
1-2.1快閃記憶體管理相關文獻回顧 4
1-2.2固態硬碟架構與平行化控制相關文獻回顧 5
1-2.3 固態硬碟效能評比相關文獻 8
1-2.4 多處理器系統晶片相關文獻 9
1-3論文結構 9
第二章、固態硬碟相關原理 10
2-1 快閃記憶體特殊特性與控制原理 10
2-1.1寫入控制 15
2-1.2讀取控制 16
2-1.3 抹除控制 18
2-2 FTL(Flash Translation Layer) 19
2-3 固態硬碟控制器架構 25
第三章、多核心固態硬碟控制器 26
3-1 多處理器系統晶片(MPSoC)架構 26
3-2 位址空間安排及資料一致性 28
3-3 分散式控制演算法 33
3-3.1 分散式寫入控制 33
3-3.2 分散式讀取控制 37
3-4 示範實例 39
第四章、系統實作與驗證 42
4-1 控制器模擬實驗 42
4-1.1 固態硬碟模擬器平台 42
4-1.2 實驗結果與分析 45
4-2 系統實作 49
4-2.1 多核心系統晶片(MPSoC)設計 49
4-2.2 實驗平台介紹 52
4.3、控制器效能評比 54
第五章、結論 56
5-1 結論 56
5-2 未來展望 56
參考文獻 57

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指導教授

陳慶瀚(Ching-han Chen)

審核日期

2009-7-7

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