博碩士論文 965302005 詳細資訊


姓名 王士銘(Shih-Ming Wang)  查詢紙本館藏   畢業系所 資訊工程學系在職專班
論文名稱 Gigabit乙太網路的UDP/IP硬體加速器設計
(Design of UDP/IP Hardware Accelerator for Gigabit Ethernet)
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摘要(中) 在網路化嵌入式系統中,網路運算通常佔用處理器大量的計算資源。尤其在Gigabit等級以上的嵌入式網路系統,由於速度和功耗的問題,已不適合用嵌入式軟體的方式在MCU或DSP上實現。因此本研究致力於設計一個UDP/IP硬體加速器,以便有效降低系統的計算負擔並提升高速網路整體效率。
本論文採用MIAT嵌入式硬體方法論來設計UDP/IP硬體加速器,包含管線化的傳送及接收控制器以及可儲存一組連線的表格,連線資訊可以透過遠端以封包指令修改。系統先以IDEF0進行階層式模組化的分析,使底層的每一個模組皆可以獨立運作,並透過GRAFCET工具為每一個獨立的模組進行離散事件建模,再以VHDL硬體描述語言合成其硬體電路。我們於FPGA完成每個模組的功能性驗證。整體系統使用了1404個Logic Elements,傳送速度達 137.14 MB/s,接收速度為173.10MB/s,可滿足Gigabit的嵌入式網路應用系統的效能需求。最後搭配市售的Gigabit MAC與PHY進行嵌入式系統整合驗證和性能測試。本研究成果將來可以應用在高速的遠端視訊監控等網路多媒體應用或是高資料流的網路遊戲應用。
摘要(英) In networked embedded systems. Network computing usually takes a lot of computing resources of processor. Grade and above, especially in embedded Gigabit Network System, Because of the speed and power consumption issues, It is not suitable to use embedded software to achieve in the MCU or DSP. Therefore, this research is to design a UDP / IP hardware accelerator. In order to reduce the computational overhead and improve the system overall efficiency of high-speed network. In this thesis, we use MIAT methodology to design an embedded hardware UDP / IP hardware accelerator. Which including pipelined transmitter and receiver controllers, and a connection table which can store information of current connection. Connection information can be modified by instructions inside UDP package sent by remote side, First we analysis whole system with hierarchical modular IDEF0, each module can operate independently, then we perform discrete event modeling on each module by GRAFCET. Finally we write VHDL hardware description language code to synthesis GRAFCET into hardware circuit, we complete functional verification for each module in FPGA. The whole system uses a 1404 Logic Elements, transmit speed up to 137.14 MB/s, receive is 173.10MB/s. With a commercially available Gigabit MAC and PHY for Embedded system, we experiment the integration and performance verification test. The results of this study can be used in future high-speed remote video monitoring network multimedia applications or high data flow applications online games.
關鍵字(中) ★ 網路協定
★ 協定加速器
★ UDP加速器
關鍵字(英) ★ UDP offload engine
★ UDP/IP offload engine
★ offload engine
論文目次 摘要 ii
ABSTRACT iii
誌謝 iv
目 錄 v
第一章 緒論 1
1.1 研究動機與目標 1
1.2 文獻探討 1
1.3 論文結構 3
第二章 嵌入式UDP/IP 4
2.1 開放式系統互聯分層模型 4
2.2 TCP/IP參考模型 5
2.3 檢查碼 6
2.4 網際網路通訊協定 7
2.5 使用者資料包通訊協定 9
第三章 實作 12
3.1 IDEF0 12
3.2 GRAFCET 15
3.3 VHDL合成規則 18
3.4 系統架構 19
3.3 可重新組態的連線表 23
3.4 UDP封包產生模組 24
3.5 IP封包產生模組 27
3.6 IP封包檢查模組 30
3.7 UDP封包檢查模組 31
3.8 傳送控制器的管線化控制模組 33
3.9 接收管線化控制模組 35
第四章 系統整合與驗證 37
4.1 MIAT-C3X實驗板 37
4.2 LAP-C(16128) 邏輯分析儀 38
4.3 UDP/IP硬體加速器電路合成 39
4.3.1 傳送控制器 39
4.3.2 接收控制器 40
4.4實驗結果 42
4.4.1 UDP封包產生器 43
4.4.2 IP封包產生器 44
4.4.3 UDP/IP傳送控制器 45
第五章 結論 47
參考文獻 49
參考文獻 [1] CHEN, Ching-Han; DAI, Jia_Hong, “Design and high-level synthesis of discrete-event controller”, National Conference of Automatic Control and Mechtronics System, vol.1, pp. 610–615, 2002
[2] 郭家銘,“模糊系統高階合成”,義守大學電機工程學系碩士學位論文,2001
[3] 杜金鴻,“機率神經網路之系統設計與高階合成”, 義守大學電機工程學系碩士學位論文,2003
[4] Herrmann, F.L.; Perin, G.; de Freitas, J.P.J.; Bertagnolli, R.; dos Santos Martins, J.B.; “AN UDP/IP NETWORK STACK IN FPGA”, Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on Digital Object Identifier: 10.1109/ICECS.2009.5410757, pp. 836 – 839, 2009
[5] Nikolaos Alachiotis, Simon A. Berger,Alexandors Stamatakis, “EFFICIENT PC-FPGA COMMUNICATION OVER GIGABIT ETHERNET”, 2010
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[7] V.Vishwanath, P.Balaji, W. Feng, J. Leigh and D.K. Panda. "A Case for UDP Offload Engines in LambdaGrids," Fourth International Workshop on Protocols for Fast Long- Distance Networks (PFLDnet 2006), Nara, Japan, February 2-3, 2006
[8] TCP/IP Protocol Suite (3rd Edition) by Behrouz A. Forouzan, Sophia Chung Fegan (ISBN:0072460601)
[9] J. Postel, ”Internet Protocol,” RFC 791 (Standard), In-ternet Engineering Task Force, September 1981. (Up-dated by RFC 1349).
[10] J. Postel, ”User Datagram Protocol,” RFC 768 (Stan-dard), Internet Engineering Task Force, August 1980.
[11] Mayer, R.J.;“IDEF0 Function Modeling”, Air Fprce Systems Command, May, 1992.
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[14] David, R.;“Grafcet :A powerful tool for specification of logic controllers”, IEEE Trans on control systems technology, Vol.3, No 3, p253-268,1995.
[15] Linkens, D.A.; Tanyi, E.B.;“Design and implementation of a hybrid modeling and simulation strategy for integrated control”, IEEE Computer-Aided Control System Design, pp 352-357,1996.
[16] Ross, D.T.;“Applications and Extensions of SADT”, IEEE,pp.23-34,1985.
[17] Petri, C. A., Kommunikation mit Automaten, Schriften des Rheinisch, Westfalischen Institutes fur Intrumentelle Mathematik and Der Universitat Bonn, 1962, translation bt Greene, C. F. Applied Data Research Inc., Suppl. 1 to Tech Report RADC-TR-65-337, N.Y.,1965.
指導教授 陳慶瀚(Ching-Han Chen) 審核日期 2010-7-28
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