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姓名 張競升(Jing-sheng Jhang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 低記憶體需求及效能改善的低密度同位元檢查碼解碼器架構
(A Low Memory Demand and Performance Enhancement Architecture of LDPC Decoder)
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摘要(中) 低密度同位元檢查(low density parity check, LDPC)解碼演算法是使用訊息傳遞(message passing)的方式進行疊代運算。在解碼效能與硬體複雜度的取捨之下,大多採用部分平行(partially parallel)架構,在此架構中記憶體(memory)被用來儲存交換的訊息。換言之,儲存元件在此架構中是不可或缺的。而記憶體的大小與檢查矩陣(parity check matrix, PCM)中 ”1” 的數目成正比。
部分平行架構的兩種記憶體使用方法,共享記憶體架構與獨立型記憶體架構已普遍實現於LDPC解碼器。因為儲存單元佔據了大部分的面積,如何減少儲存單元的面積成為LDPC解碼器上一個熱門的研究課題。運用移位暫存器來做資料的取回,可減少記憶體使用量,使得整體電路面積可以下降;而運用環型位移暫存器來取代記憶體以及資料取回電路,可以提升解碼速度。本論文提出改良型架構融合兩者的優點以提高吞吐量(throughput)及減低硬體需求。實驗結果顯示,所提出來的方法實現在(3,6)規則同位元檢查矩陣,編碼長度(code length)為 1536位元(bit),編碼率(code rate) 1/2,所提出的解碼器在操作頻率為400Mhz時,其吞吐量可達到438Mb/s。
摘要(英) LDPC code is one of error correction codes (ECC) and widely used in digital communication systems because it has good error correcting performance for large code length. There exists a trade-off between hardware complexity and decoding efficiency on LDPC decoder. In general, partially parallel architecture is adopted for reducing the complexity of hardware implementation. Because of LDPC code decodes iteratively, storage element is necessary when designing a LDPC decoder in finite hardware cost. Since that storage element dominates the area of LDPC decoders. Reducing the area cost of memory becomes an important issue.
Previous studies provided methods to lower the memory requirement and to reduce the processing unit. Lowering the memory requirement can be achieved by using registers; on the other hand, the throughput can be enhanced by using the circular shift registers. This thesis proposes an alternative architecture which takes the advantages of both approaches. The proposed architecture attempts to achieve higher throughout at moderate hardware cost. Results show that, for a (3,6)-regular parity check matrix (PCM) with code length 1536, the proposed LDPC decoder achieves a throughput of 438Mb/s at operating frequency of 400MHz.
關鍵字(中) ★ 部分平行
★ 低密度同位元碼
★ 低密度同位元解碼器
關鍵字(英) ★ LDPC code
★ LDPC decoder
★ paritally parallel
論文目次 一、緒論..................................................1
1.1數位通訊與錯誤更.......................................1
1.2研究動機...............................................2
二、研究背景..............................................4
2.1同位元檢查矩陣.........................................4
2.2類循環(quasi-cyclic)矩陣...............................6
2.3 LDPC編碼原理..........................................7
2.4 LDPC 解碼.............................................8
2.4.1 訊息傳遞演算法(Message Passing Algorithm, MPA)......8
2.4.2 積和演算法(Sum Product Algorithm, SPA)[3]..........13
2.2.2對數型積和演算法(Log-Likelihood Ratio for SPA)......16
2.2.3最小和演算法與改良型最小和演算法....................18
2.2.4位元錯誤率與疊代關係模擬............................19
三、解碼器硬體架構.......................................20
3.1 LDPC解碼架構.........................................20
3.1.1完全平行架構(Fully parallel Architecture)...........20
3.1.2序列架構(Serial Architecture).......................21
3.1.3部分平行架構(Partially Parallel Architecture).......22
3.1.4探討與比較..........................................24
3.2CNFU與BNFU架構........................................25
3.2.1對數型積和演算法硬體架構............................25
3.2.2最小和演算法與改良型最小和演算法硬體架構............27
3.3以記憶體為基礎所實現的部分平行架構[19]................28
3.3.1修正型最小和演算法..................................28
3.3.2硬體架構............................................31
3.3.3記憶體排列方式......................................32
3.3.4資料取回結構問題....................................34
3.3.5吞吐量估計..........................................37
3.4以環型移位暫存器為基礎的部分平行架構[20]..............38
3.4.1資料取回與儲存架構..................................38
3.4.2硬體架構............................................39
3.4.3 CSR演算法..........................................40
3.4.4 吞吐量估計.........................................42
3.5 討論與比較...........................................42
四、提出的架構設計與電路實現.............................44
4.1 改良型架構...........................................44
4.1.1原型架構............................................44
4.1.2所提出的解碼架構....................................46
4.2 解碼流程與改良型CSR演算法............................49
4.2.1解碼流程............................................49
4.2.2改良型CSR演算法.....................................50
4.3整體架構與功能單元....................................57
4.3.1整體解碼架構(Overall decoding architecture).........57
4.3.2處理單元(Process Unit, PU)..........................58
4.3.3數值產生器(value generator, VG).....................61
4.3.4提出的記憶體排列方式................................61
4.3.5環型位移暫存器(Circular Shift Register, CSR)........63
4.4實驗結果(Experimental Results)........................63
五、結論與未來工作.......................................68
5.1結論..................................................68
5.2未來工作..............................................69
參考文獻.................................................70
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指導教授 魏慶隆(Chin-long Wey) 審核日期 2010-8-24
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