具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：39

、訪客IP：18.119.123.32

姓名

涂祐豪(Yo-hao Tu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器
(A Wide Range Delay-Locked Loop with Phase Error Calibration and Frequency Multiplier)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文提出一個具寬頻操作、擁有多個相位輸出並具有相位誤差較正電路的延遲鎖定迴路。為了得到更大的運用效能，還具有一個頻率倍頻器可以另外產生一個倍頻的時脈訊號。在延遲鎖定迴路中，利用多頻段技巧，使電路可以操作在較寬的操作頻帶之下。而為了減少因為靜態相位誤差帶來的效應，利用一個時間放大器所組成的校正迴路，可以達到修正相位誤差的效果。延遲鎖定迴路整體電路架構若要操作在高速之下，在設計上有一定的難度，故將架構中的多相位輸出，透過邊緣合成的技巧，即可得到一個高速的時脈訊號，而延遲鎖定迴路本身卻可以保持較低速的操作頻率。另外，延遲鎖定迴路之多相位輸出可提供給發射端電路(Transmitter, Tx)使用，作為其時脈產生器。
　　本論文之具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器使用TSMC 180 nm 1P6M CMOS製程實現晶片，其操作頻率範圍可從80 MHz到600 MHz，並且擁有12個相位的輸出，而頻率倍頻器範圍可從0.96 GHz 到 2.5 GHz。整體晶片面積為745 × 745 um2，核心電路的面積為356 × 356 um2。電路在操作電壓為1.8 V時，最大功率消耗為19.2 mW。延遲鎖定迴路輸出訊號(600 MHz)之最大抖動量(P2P Jitter)的為21.22 ps，方均根抖動量(RMS Jitter)為2.62 ps。而頻率倍頻器的輸出訊號(2.4 GHz)之最大抖動量(P2P Jitter)為35.11 ps，方均根抖動量(RMS Jitter)為4.28 ps。本論文提出的改良式責任週期校正電路和相位誤差補償迴路皆能有效的操作，並且相位誤差可以得到約 33.33 % 的改善。

摘要(英)

This study presents a wide-range and multiphase DLL-based clock generator with the Phase Error Compensation loop. For more applications, we proposed a frequency multiplier to synthesize a combined clock. In this voltage control delay line, we take the multi-gain technique to achieve the wide-range operation frequency. And we proposed a Phase Error Compensation loop with the timing amplifier. It is difficult to realize a DLL in high operation frequency, so using multiphase technique can solve this problem. And the multiphase architecture can become the clock generator of a Transmitter (Tx).
　　This study was implemented by TSMC 180 nm 1P6M CMOS process. The input frequency range of the proposed DLL is from 80 MHz to 600 MHz with 12-phase output. The output range of frequency multiplier is from 0.96 GHz to 2.5 GHz. The chip area is 0.745 × 0.745 mm2 and the core area is 0.356 × 0.356 mm2. The power consumption is 19.2 mW at a supply of 1.8 V. The peak-to-peak jitter and rms jitter of delay locked loop are 21.22 ps and 2.62 ps at 800 MHz. The peak-to-peak jitter and rms jitter of frequency multiplier are 35.11 ps and 4.28 ps at 2.4 GHz. And the Phase Error Compensation loop can improve 33.33% of the static phase error.

關鍵字(中)

★ 阻塞鎖定
★ 責任週期校正電路
★ 半穿透式架構
★ 頻率倍頻器
★ 延遲鎖定迴路

關鍵字(英)

★ Stuck Locking
★ Frequency Multiplier (FM)
★ Half Transparent (HT)
★ Duty Cycle Corrector (DCC)
★ Delay-Locked Loop (DLL)

論文目次

Abstract .......................................................................................................................... ii
目錄................................................................................................................................ iii
致謝................................................................................................................................ vi
圖目錄............................................................................................................................ vii
表目錄............................................................................................................................ ix
第1章緒論..................................................................................................................... 1
1.1 研究動機.................................................................................................................. 1
1.2 發射端電路.............................................................................................................. 2
1.3 論文架構.................................................................................................................. 4
第2章延遲鎖定迴路架構與理論................................................................................. 5
2.1 傳統類比式延遲鎖定迴路架構.............................................................................. 5
2.1.1 相位偵測器........................................................................................................... 6
2.1.2 充電幫浦與迴路濾波器....................................................................................... 7
2.1.3 電壓控制延遲線................................................................................................... 8
2.1.3.1 電阻電容時間常數控制式延遲元件................................................................ 9
2.1.3.2 可變電容式延遲元件[2] ................................................................................... 9
2.1.3.3 電流限制式延遲元件[2] ................................................................................... 10
2.1.3.4 差動對稱性負載式延遲元件............................................................................ 11
2.2 延遲鎖定迴路之理論分析...................................................................................... 12
2.2.1 錯誤鎖定............................................................................................................... 12
2.2.2 鎖定範圍............................................................................................................... 13
2.2.3 系統分析............................................................................................................... 14
2.2.4 行為模型............................................................................................................... 15
第3章改良式相位偵測器與相位誤差補償迴路......................................................... 17
3.1 介紹.......................................................................................................................... 17
3.2 半穿透架構式相位偵測器問題探討...................................................................... 17
3.2.1 半穿透架構式相位偵測器................................................................................... 17
3.2.2 半穿透架構式相位偵測器的錯誤狀況............................................................... 18
3.3 改良式相位偵測器.................................................................................................. 21
3.3.1 改良式責任週期校正電路(MDCC) .................................................................... 21
3.3.2 具有改良式責任週期校正電路的相位偵測器................................................... 22
3.4 相位誤差補償.......................................................................................................... 26
3.4.1 時間放大器........................................................................................................... 26
3.4.2 相位誤差補償電路............................................................................................... 28
第4章具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器......................... 31
4.1 介紹.......................................................................................................................... 31
4.2 電路架構與系統分析.............................................................................................. 32
4.3 電路設計.................................................................................................................. 33
4.3.1 充電幫浦............................................................................................................... 33
4.3.2 電壓控制延遲線................................................................................................... 34
4.3.3 頻率倍頻器........................................................................................................... 38
4.3.4 跳段機制............................................................................................................... 40
4.3.5 拴鎖鎖定保護電路............................................................................................... 42
第5章晶片模擬與量測................................................................................................. 45
5.1 電路佈局.................................................................................................................. 45
5.2 電路模擬.................................................................................................................. 46
5.2.1 自動跳段模擬圖................................................................................................... 46
5.2.2 多相位輸出和相位抖動模擬圖........................................................................... 48
5.3 量測環境考量.......................................................................................................... 51
5.4 晶片與印刷電路板照相.......................................................................................... 54
5.5 量測結果.................................................................................................................. 55
5.6 規格比較.................................................................................................................. 59
第6章結論與未來研究方向......................................................................................... 61
6.1 結論.......................................................................................................................... 61
6.2 未來研究方向.......................................................................................................... 61
參考文獻........................................................................................................................ 62

參考文獻

[1] M.J. Lee, W.J. Dally, J.W. Poulton, P. Chiang, and S.F. Greenwood, “An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications, “in Symp. VLSI Circuits Dig., June 2001 , pp.145-152.
[2] T.H. Su, “ Design of a CMOS Delay-Locked Loop based programmable frequency multiplier＂ Master Thesis, National Dong-Hwa University, July. 2005.
[3] [J.G. Maneatis, “ Low-jitter process-independent DLL and PLL based on self-biased techniques, ＂ IEEE J. Solid-State Circuit, vol. 31, no. 11, pp. 17823-1732, Nov. 1996.
[4] MEAD Microelectronics Inc., “Lecture notes for phase-locked loops, oscillators, and frequency synthesizer,＂ 1998.
[5] H.H. Chang, J.W. Lin, C.Y. Yang, and S.I. Liu, “A wide-range Delay-Locked Loop with a fixed latency of one clock cycle,＂ IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1021-1027, Aug. 2002.
[6] 劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006
[7] C.N. Chuang, and S.I. Liu, “A 0.5-5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump,＂ IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 11, pp. 939-943, Nov. 2007.
[8] C.C. Chen, and S.I. Liu, “An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Lin,＂ IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2413-2421, Nov. 2008.
[9] Y.S. Kim, “A 40-to-800MHz Locking Multi-Phase DLL＂ IEEE ISSCC, Feb. 2007, pp. 306-307.
[10] R.J. Yang and S.I. Liu, “ A 40 – 550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm, ＂ IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 361-373, Feb. 2007.
[11] S. Hoyos, “A 15 MHz-600 MHz, 20mW, 0.38mm2, Fast Coarse Locking Digital DLL in 0.13um CMOS＂, IEEE European Solid-State Circuits Conference, Sep. 2008, pp. 90-93.
[12] H.H. Chang, J.Y. Chang, C.Y. Kuo, and S.I. Liu, “A 0.7-2-GHz self-calibrated multiphase Delay-Locked Loop,＂ IEEE J. Solid-State Circuits, vol. 41, no. 5, May. 2006.
[13] T.T. Liu and C.K. Wang, “A 1-4GHz DLL based low-jitter multi-phase clock generator for low-band ultra-wideband application, ＂ IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Aug. 2004 , pp. 330-333.
[14] J. Yuan and C. Svensson, “Fast CMOS nonbinary divider and counter,＂Electronic Letters, vol. 29, pp. 1222-1223, June, 1993.
[15] A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,＂ IEEE J. Solid-State Circuits, vol.34, no.6, pp. 790-804, June. 1999.
[16] Y. Moon, J. Choi, K. Lee, D.K. Jeong, and M.K. Kim, “An all-analog multiphase Delay-Locked Loop using a replica delay line for wide-range operation and low-jitter performance＂ IEEE J. Solid-State Circuits, vol.35, no.3, pp. 377-384, Mar. 2000.
[17] G. Chien and P.R. Gray, “A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications,＂ IEEE J. Solid-State Circuits, vol.35, no.12, pp. 1996-1999, Dec. 2000.
[18] R.L. Aguiar and D.M. Santos, “Oscillatorless clock multiplication,＂ IEEE International Symposium on Circuits and Systems, May. 2001, pp. 630-633.
[19] C. Kim, I.C. Hwang, and S.M. Kang, “A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator,＂ IEEE J. Solid-State Circuits, vol.37, pp. 1414-1420, Nov. 2002.
[20] R.M. Weng, T.H. Su, C.Y. Liu, and Y.F. Kuo, “A CMOS Delay-Locked Loop based frequency multiplier for wide-range operation, ＂ IEEE International Symposium on Circuits and Systems, Dec. 2005 , pp. 419-422.
[21] K.H. Cheng, S.M. Chang, S.Y. Jiang, and W.B. Yang, “A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit, ＂ IEEE International Symposium on Circuits and Systems, vol.2, May. 2005 , pp.
1174-1177.
[22] T.C. Lee and K.J. Hsiao, “The design and analysis of a DLL-based frequency synthesizer for UWB application, ＂ IEEE J. Solid-State Circuits, vol.6, pp. 1245-1252, June. 2006.
[23] J.H. Kim, Y.H. Kwak, M.Y. Kim, S.W. Kim, and C. Kim, ＂A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling,＂ IEEE J. Solid-State Circuits, vol. 41, no.9, Sep. 2006.
[24] C.H. Chen, “A fast-locking and low-jitter all digital Delay Locked Loop＂ Master Thesis, National Chung Cheng University, July. 2003.
[25] T.H. Su, “ Design of a CMOS Delay-Locked Loop based programmable frequency multiplier＂ Master Thesis, National Dong-Hwa University, July. 2005.

指導教授

鄭國興(Kuo-hsing Cheng)

審核日期

2010-10-19

推文