博碩士論文 975201027 詳細資訊


姓名 陳亭如(Ting-Ju Chen)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 三維系統級封裝晶片之記憶體的測試與修復
(Testing and Repair of Memories in 3D-SiP Chips)
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 對於整合不同製程的元件,系統級封裝 (System-in-Package, SiP) 整合技術將為其有效的解決方法。在典型的系統級封裝晶片中,不同類別的裸晶將透過打線 (bonding wire) 相互堆疊和連接。其中,記憶體裸晶為廣泛使用的裸晶之一。不同類別的記憶體裸晶都可能整合於一個系統級封裝晶片中。然而,由於大部分記憶體裸晶的輸入/輸出腳位都無法直接透過封裝晶片的輸入/輸出腳位做存取,倘若在後封裝階段 (post-packaging phase) 欲使用自動測試設備 (external automatic test equipment, ATE) 測試這些記憶體裸晶將非常困難。因此,發展應用於後封裝階段有效的測試技術為必要的。顯然地,在系統級封裝設計上內建自我測試 (built-in self-test, BIST) 技術為測試記憶體裸晶的有效方法。
論文的第一部分,提出一個可程式化的內建自我測試方法用於測試系統級封裝晶片中系統晶片 (System-in-Chip, SoC) 裸晶的 SRAM、Flash 記憶體裸晶和 SDRAM 裸晶。在 SDRAM 的測試上,提出一個測試程序用以有效的降低記憶體的測試時間。並且,提出一個應用於 SDRAM 執行突爆模式 (burst mode) 測試時,特定的測試診斷方法。所提出可程式化內建自我測試方法具有高測試診斷能力、高可攜性、可平行測試和低測試複雜度的優點。由實驗結果觀察可知,在系統晶片具有兩個 SRAM (512K-bit SRAM 和 1M-bit SRAM) 和一個 256M-bit Flash 裸晶的情形下,所提出可程式化內建自我測試電路的面積涵蓋率只為 0.07%。
論文的第二部分,提出一個可改變取樣大小的適應性徵狀壓縮演算法,將有效降低診斷資料輸出時間和 ATE 的儲存容量。由實驗結果觀察可知,在系統級封裝晶片中所提出可程式化內建自我測試電路結合上適應性徵狀壓縮器,在系統晶片具有兩個 SRAM (512K-bit SRAM 和 1M-bit SRAM) 和一個 256M-bit Flash 裸晶的情形下,電路的面積涵蓋率只為 0.08%。
論文第三部分,提出一個可重組的內建備份元件分析器 (built-in redundancy analyzer, BIRA),所提出的方法只需一次測試流程且使用非常低的面積成本達到最佳修復效率。此外,提出的層級式緩衝器將用來萃取錯誤字組中多個錯誤位元,如此,便能支援字組導向記憶體執行同速測試與備份元件分析。由實驗結果觀察可知,所提出可重組內建備份元件分析方法在實現上面積成本較現存方法低。
摘要(英) System-in-Package (SiP) integration technology provides a good solution for integrating components with different technologies. In an SiP, typically, various types of dies are stacked and connected with bonding wires. Among those dies, memory die is one widely used die. Furthermore, different types of memory dies may be integrated in the SiP. Using external automatic test equipment (ATE) to test these memory dies in the post-packaging phase becomes very difficult, since the I/O terminals of most of these memory dies cannot be directly accessed through the I/O pins of the package. Effective test techniques for testing these memory dies in the post-packaging phase thus should be developed. Apparently, built-in self-test (BIST) technique is a good solution for testing the memory dies in SiP designs.
In the first part of this thesis, a programmable BIST scheme is proposed to test the SRAMs in a System-on-Chip(SoC) die, Flash memory dies, and SDRAM dies in an SiP chip. For the testing of SDRAMs, an efficient test procedure is proposed to reduce the testing time. Also, a specific diagnosis approach is proposed to diagnose the SDRAM when it is tested in burst mode. The proposed BIST scheme has the advantages of high diagnosability, high portability, parallel test, and low test complexity. Experimental results show that the area overhead of the proposed BIST circuit for one 512K-bit SRAM and one 1M-bit SRAM in an SoC die, and one 256M-bit Flash die is only about 0.07%.
In the second part of this thesis, an adaptive syndrome compression algorithm for variable-size symbols is proposed to reduce the diagnostic data exportation time and the storage requirement of ATE. Experimental results show that the area overhead of the proposed BIST circuit with the adaptive syndrome compressor for an SiP with one SoC die in which one 512K-bit SRAM and one 1M-bit SRAM are embedded, and one 256M-bit Flash memory die is only about 0.08%.
In the third part of this thesis, a reconfigurable built in redundancy analyzer (ReBIRA) scheme which can provide the optimal repair efficiency using very low area cost and one test run is proposed. In addition, a level- based buffer is proposed to extract multiple-bit failure of a faulty word to support the at-speed test and redundancy analysis for word-oriented RAMs. Experimental results show that the area cost for implementing the proposed ReBIRA scheme is much lower than that of existing works.
關鍵字(中) ★ 診斷資料壓縮
★ 記憶體內建自我修復
★ 記憶體內建自我測試
關鍵字(英) ★ Memory Built-In Self-Test
★ Memory Built-In Self-Repair
★ Diagnostic Data Compression
論文目次 1 Introduction 1
1.1 Test Flow of System-in-Package Chips 1
1.2 Built-In Self-Repair Techniques 3
1.3 Memory Testing Issues of SiP Chips 8
1.4 Targeted Fault Models 9
1.5 Thesis Motivations and Contributions 10
1.6 Thesis Organization 13
2 Built-In Self-Test Scheme with Diagnosis Ability for Memories in SiP Chips 14
2.1 Proposed Programmable BIST Scheme 14
2.1.1 Programmable BIST Architecture 14
2.1.2 Design of the TPG 17
2.1.3 Test Interfaces for Flash and SDRAM Testing 19
2.2 SRAM Testing 21
2.3 SDRAM Testing 22
2.3.1 Speed Grading and Data Retention Test 22
2.3.2 Testing Time Reduction Technique 22
2.3.3 Diagnosis Feature 26
2.4 Flash Memory Testing 27
2.5 Interconnection Testing 28
2.6 Experimental Results and Analysis 31
3 Adaptive Diagnostic Syndrome Compression Scheme for RAMs 35
3.1 Introduction to Diagnostic Syndrome Compression Scheme 35
3.2 An Adaptive Diagnostic Syndrome Compression Scheme 37
3.3 Experimental Results and Analysis 43
4 Built-In Self-Repair Scheme for RAMs in SiP Chips 48
4.1 A Built-In Redundancy-Analysis Scheme with Optimal Repair Efficiency for RAMs 48
4.1.1 The Proposed At-Speed ReBIRA Scheme 48
4.1.2 Design of the Proposed At-Speed ReBIRA Circuit 54
4.1.3 Experimental Results and Analysis 65
4.2 BISR Scheme for External DRAMs in SiP Chips 76
4.2.1 Architecture of Address Remapping Unit for External DRAMs 77
5 Conclusion and Future Work 79
5.1 Conclusion 79
5.2 Future Work 80
Bibliography 81
參考文獻 [1] D. Applleo, P. Bernardi, M. Grosso, and M. S. Reorda, “System-in-package testing: problems and solutions,” IEEE Design & Test of Computers, vol. 23, no. 3, pp. 203–211, May-July 2006.
[2] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs,” in Proc. Int’l Test Conf. (ITC), 2000, pp. 567-574.
[3] J.-D. Yu, J.-F. Li, and T.-W. Tseng, “Testing crosstalk faults of data and address busses in embedded RAMs,” in IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, April 2007, pp. 91–94.
[4] K. Yamasaki, I. Suzuki, A. Kobayashi, K. Horie, Y. Kobayashi, H. Aoki, H. Hayashi, K. Tada, K. Tsutsumida, and K. Higeta, “External memory BIST for system-in-package,” in Proc. Int’l Test Conf. (ITC), Austin, Nov. 2005, pp. 1–10.
[5] R. R. Tummala, “SOP: what is it and why? A new microsystem-integration technology paradigm-Moore’s law for system integration of miniaturized convergent systems of the next decade,” IEEE Trans. Advanced Packaging, vol. 27, no. 2, pp. 241–249, May 2004.
[6] W. Krenik, D. D. Buss, and P. Rickert, “Cellular handset integration-SIP versus SOC,”IEEE Jour. of Solid-State Circuits, vol. 40, no. 9, pp. 1839–1846, Sept. 2005.
[7] B. C. Kim and Y. Zorian, “Guest editors’ introduction: big innovations is small packages,”IEEE Design & Test of Computers, vol. 23, no. 3, pp. 186–187, May-July 2006.
[8] A. Maurelli, D. Belot, and G. Campardo, “SoC and SiP, the Yin and Yang of the Tao for new electronic era,” Proceedings of the IEEE, vol. 97, no. 1, pp. 9–17, Jan. 2009.
[9] F. P. Carson, Y. C. Kim, and I. S. Yoon, “3-D stacked package technology and trends,”Proceedings of the IEEE, vol. 97, no. 1, pp. 31–42, Jan. 2009.
[10] R. Rajsuman, “RAMBIST builder: A methodology for automatic built-in self-test design of embedded RAMs,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), San Jose, 1996, pp. 50–56.
[11] J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, “Processor-based built-in self-test for embedded DRAM,” IEEE Jour. of Solid-State Circuits, pp. 1731–1740, Nov. 1998.
[12] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, “A programmable BIST core for embedded DRAM,” IEEE Design & Test of Computers, vol. 16, no. 1, pp. 59–70, Jan.-Mar. 1999.
[13] R. Rajsuman, “Design and test of large embedded memories: an overview,” IEEE Design & Test of Computers, vol. 18, no. 3, pp. 16–27, May 2001.
[14] K.-L. Cheng, C.-M. Hsueh, J.-R. Huang, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, “Automatic generation of memory built-in self-test cores for system-on-chip,” in Proc. Tenth IEEE Asian Test Symp. (ATS), Kyoto, Nov. 2001, pp. 91–96.
[15] M. L. Bodoni, A. Benso, S. Chiusano, S. D. Carlo”, G. D. Natale”, and P. Prinetto,“An effective distributed BIST architecture for RAMs,” in Proc. IEEE European Test Workshop (ETW), 2000, pp. 119–124.
[16] Y. Zorian and S. Shoukourian, “Embedded-memory test and repair: Infrastructure IP for SoC yield,” IEEE Design & Test of Computers, vol. 20, pp. 58–66, May-June 2003.
[17] B. H. Fang and N. Nicolici, “Power-constrained embedded memory BIST architecture,”in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Boston, Nov. 2003, pp. 451–458.
[18] R. C. Aitken, “A modular wrapper enabling high speed BIST and repair for small wide memories,” in Proc. Int’l Test Conf. (ITC), Charlotte, Oct. 2004, pp. 997–1005.
[19] L.-M. Denq and C.-W. Wu, “A hybrid BIST scheme for multiple heterogeneous embedded memories,” in IEEE Asian Test Symp. (ATS), Beijing, Oct. 2007, pp. 349–354.
[20] J.-C. Yeh, K.-L. Cheng, Y.-F. Chou, and C.-W.Wu, “Flash memory testing and built-in self-diagnosis with march-like test algorithms,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 6, pp. 1101–1113, June 2007.
[21] Y. Zorian, “Embedded memory test & repair: Infrastructure IP for SOC yield,” in Proc. Int’l Test Conf. (ITC), Baltmore, Oct. 2002, pp. 340–349.
[22] I. Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lweandowski, “Built in self repair for embedded high density SRAM,” in Proc. Int’l Test Conf. (ITC), Oct. 1998, pp. 1112–1119.
[23] V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words,” in Proc. Int’l Test Conf. (ITC), Baltimore, Oct. 2001, pp. 995–1001.
[24] S. Nakahara, K. Higeta, M. Kohno, T. Kawamura, and K. Kakitani, “Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm,” in Proc. Int’l Test Conf. (ITC), 1999, pp. 301–310.
[25] D. K. Bhavsar, “An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264,” in Proc. Int’l Test Conf. (ITC), Atlantic City, Sept. 1999, pp. 311–318.
[26] D. Xiaogang, S. M. Reddy, W.-T. Cheng, J. Rayhawk, and N. Mukherjee, “At-speed built-in self-repair analyzer for embedded word-oriented memories,” in International Conference on VLSI Design, 2004, pp. 895–900.
[27] M. Nicolaidis, N. Achouri, and S. Boutobza, “Dynamic data-bit memory built-in selfrepair,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2003, pp. 588–594.
[28] C.-L. Su, R.-F. Huang, and C.-W. Wu, “A processor-based built-in self-repair design for embedded memories,” in Proc. 12th IEEE Asian Test Symp. (ATS), Xian, Nov. 2003, pp. 366–371.
[29] R. C. Aitken, “Applying defect-based test to embedded memories in a COT model,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), San Jose, July 2003, pp. 72–77.
[30] M. Nicolaidis, N. Achouri, and L. Anghel, “A diversified memory built-in self-repair approach for nanotechnologies,” in Proc. IEEE VLSI Test Symp. (VTS), Napa Valley, Apr. 2004, pp. 313–318.
[31] C.-L. Su, Y.-T. Yeh, and C.-W.Wu, “An integrated ECC and redundancy repair scheme for memory reliability enhancement,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Monterey, CA, Oct. 2005, pp. 81–89.
[32] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair design for RAMs with 2-D redundancies,” IEEE Trans. on VLSI Systems, vol. 13, no. 6, pp. 742–745, June 2005.
[33] S.-K. Lu, Y.-C. Tsai, C.-H. Hsu, K.-H. Wang, and C.-W. Wu, “Efficient built-in redundancy analysis for embedded memories with 2-D redundancy,” IEEE Trans. on VLSI Systems, vol. 14, no. 1, pp. 34–42, Jan. 2006.
[34] T.-W. Tseng, J.-F. Li, C.-C. Hsu, A. Pao, K. Chiu, and E. Chen, “A reconfigurable built-in self-repair scheme for multiple repairable RAMs in SOCs,” in Proc. Int’l Test Conf. (ITC), Santa Clara, Oct 2006, Paper 30.2, pp. 1–8.
[35] T.-W. Tseng, C.-H. Wu, Y.-J. Huang, J.-F. Li, A. Pao, K. Chiu, and E. Chen, “A built-in self-repair scheme for multiport RAMs,” in Proc. IEEE VLSI Test Symp. (VTS), Berkeley, May 2007, pp. 355–360.
[36] C.-D. Huang, J.-F. Li, and T.-W. Tseng, “ProTaR: An infrastructure IP for repairing RAMs in SOCs,” IEEE Trans. on VLSI Systems, vol. 15, no. 10, pp. 1135–1143, Oct. 2007.
[37] P. Ohler, S. Hellebrand, and H.-J. Wunderlich, “An integrated built-in test and repair approach for memories with 2D redundancy ,” in IEEE European Test Symposium (ETS), Freiburg, May 2007, pp. 91–96.
[38] W. Jeong, I. Kang, K. Jin, and S. Kang, “A fast built-in redundancy analysis for memories with optimal repair rate using a line-based search tree,” IEEE Trans. On VLSI Systems, vol. 17, pp. 1665–1678, Dec. 2009.
[39] J. Chung, J. Park, J. A. Abraham, E. Byun, and C.-J. Woo, “Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate,” in Proc. IEEE VLSI Test Symp. (VTS), Apr. 2010, pp. 33–38.
[40] M.-H. Yang, H. Cho, W. Kang, and S. Kang, “EOF: Efficient built-in redundancy analysis methodology with optimal repair rate,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 7, pp. 1130–1135, July 2010.
[41] S.-Y. Kuo and W. K. Fuchs, “Efficient spare allocation in reconfigurable arrays,” IEEE Design & Test of Computers, vol. 4, no. 1, pp. 24–31, Feb. 1987.
[42] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancy analysis for memory yield improvement,” IEEE Trans. on Reliability, vol. 52, no. 4, pp. 386–399, Dec. 2003.
[43] R. Dekker, F. Beenker, and L. Thijssen, “A realistic fault model and test algorithm for static random access memories,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 6, pp. 567–572, June 1990.
[44] J.-F. Li, R.-S. Tzeng, and C.-W. Wu, “Diagnostic data compression techniques for embedded memories with built-in self-test,” Jour. of Electronic Testing: Theory and Applications, vol. 18, no. 4-5, pp. 515–527, Aug.-Oct. 2002.
[45] S.-C. Shen, “A low cost memory built-in self-test architecture and its design automation,” Master Thesis, Dept. Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, July 2005.
[46] A. J. van de Goor, I. B. S. Tlili, and S. Hamdioui, “Converting march tests for bit-oriented memories into tests for word-oriented memories,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), San Jose, Aug. 1998, pp. 46–52.
[47] A. J. van de Goor and I. B. S. Tlili, “March tests for word-oriented memories,” in Proc.Conf. Design, Automation, and Test in Europe (DATE), 1998, pp. 501–508.
[48] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Fault simulation and test algorithm generation for random access memories,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 4, pp. 480–490, Apr. 2002.
[49] C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES: A fast memory fault simulator,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Albuquerque, Nov. 1999, pp. 165–173.
[50] M. G. Mohammad and K. K. Saluja, “Flash memory disturbances: Modeling and test,” in Proc. IEEE VLSI Test Symp. (VTS), Marina Del Rey, California, Apr. 2001, pp. 218–224.
[51] M. G. Mohammad, K. K. Saluja, and A. Yap, “Fault models and test procedures for flash memory disturbances,” Jour. of Electronic Testing: Theory and Applications, vol. 17, pp. 495–508, 2001.
[52] J.-C. Yeh, C.-F. Wu, K.-L. Cheng, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, “Flash memory built-in self-test using march-like algorithms,” in Proc. IEEE Int’l Workshop on Electronic Design, Test, and Applications (DELTA), Christchurch, Jan. 2002, pp. 137–141.
[53] J.-C. Yeh, Y.-T. Lai, Y.-Y. Shih, and C.-W. Wu, “Flash memory built-in self-diagnosis with test mode control,” in Proc. IEEE VLSI Test Symp. (VTS), Palm Springs, May 2005, pp. 15–20.
[54] N. Jarwala and C. W. Yau, “A new framework for analyzing test generation and diagnosis algorithm for wiring interconnects,” in Proc. Int’l Test Conf. (ITC), 1989, pp. 63–70.
[55] R.-F. Huang, C.-L. Su, C.-W. Wu, Y.-J. Chang, and W.-C. Wu, “A memory built-in self-diagnosis design with syndrome compression,” in Proc. IEEE Int’l Workshop on Current & Defect Based Testing (DBT), Napa Valley, Apr. 2004, pp. 97–102.
[56] C.-L. Su, R.-F. Huang, C.-W. Wu, Y.-J. Chang, and S.-T. Lin, “Embedded memory diagnostic data compression using differential address,” in Proc. Int’l Symp. on VLSI Technology, Systems, and Applications: Design, Automation and Test (VLSITSA-DAT), Hsinchu, Apr. 2005, pp. 20–23.
[57] J. T. Chen, J. Rajski, J. Khare, O. Kebichi, and W. Maly, “Enabling embedded memory diagnosis via test response compression,” in Proc. IEEE VLSI Test Symp. (VTS), Marina Del Rey, California, Apr. 2001, pp. 292–298.
[58] J. T. Chen, J. Khare, K. Walker, S. Shaikh, J. Rajski, and W. Maly, “Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring,” in Proc. Int’l Test Conf. (ITC), Baltmore, Oct. 2001, pp. 258–267.
[59] V. N. Yarmolik, S. Hellebrand, and H. Wunderlich, “Self-adjusting output data compression: An efficient BIST technique for RAMs,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), 1998, pp. 173–179.
[60] S. B. Musin, A. A. Ivaniuk, and V. N. Yarmolik, “Self-adjusting output data compression for RAM with word error detection and correction,” in International Conference on Mixed Design of Integrated Circuits and Systems, Poland, June 2007, pp. 535–538.
[61] S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, and V. N. Yarmolik, “Error detecting refreshment for embedded DRAMs,” in Proc. IEEE VLSI Test Symp. (VTS), 1999, pp. 384–390.
[62] ——, “Efficient online and offline testing of embedded DRAMs,” IEEE Trans. on Computers, vol. 51, no. 7, pp. 801–809, July 2002.
[63] N. Mukherjee, A. Pogiel, J. Rajski, and J. Tyszer, “High throughput diagnosis via
compression of failure data in embedded memory BIST,” in Proc. Int’l Test Conf. (ITC), Santa Clara, Oct. 2008, pp. 1–10.
[64] D. A. Huffman, “A method for the construction of minimum-redundancy codes,” Proc. IRE, vol. 40, pp. 1098–1101, Sept. 1952.
[65] M. Tarr, D. Boudreau, and R. Murphy, “Defect analysis system speeds test and repair of redundant memories,” Electronics, pp. 175–179, Jan. 12 1984.
[66] J. R. Day, “A fault-driven, comprehensive redundancy algorithm,” in IEEE Design & Test of Computers, vol. 2, June 1985, pp. 35–44.
[67] T.-W. Tseng, J.-F. Li, and C.-C. Hsu, “ReBISR: A reconfigurable built-in self-repair scheme for random access memories in SOCs,” IEEE Trans. on VLSI Systems, vol. 18, no. 6, pp. 921–932, June 2010.
[68] J. M. Mulder, N. T. Quach, and M. J. Flynn, “An area model for on-chip memories and its application,” IEEE Jour. of Solid-State Circuits, vol. 26, no. 2, pp. 98–106, Feb. 1991.
指導教授 李進福(Jin-Fu Li) 審核日期 2010-8-27
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡