||As the evolution of semiconductor process technology, the process variation will be more and more serious in device mismatch and wire parasitic. Layout automation is likely to play a key role in analog circuit design to prevent design errors, high complex, error-prone layout tasks, time-consuming, tedious and expensive design iterations. Poor layout due to its sensitivity to parasitic capacitance, device mismatching, process variations and gradient errors will result in both the product inaccuracy and yield loss. The performance of many types of analog circuits, like ADC, DAC, filters, etc., relies on the implementation of accurate capacitor array ratios, which are determined by properly arranging the identical unit-size capacitors and considering the effect of routing induced capacitances.|
In this thesis, a yield-aware ratio-keeping channel router is proposed for capacitor array block creation. The 4-step channel router including channel allocation, wire establishment, wire link, and plate outstretching, is performed ordinarily to balance the routing wire length and the number of wire contact via’s of the corresponding array capacitors and to reduce the parasitic capacitances due to extra insertions and overlapping. The router can be not only applied to the case of a pair of two target capacitors but also to the one of multiple target capacitors. By the conjunction of an array assignment using of spatial correlation feature, two cases are used as examples to demonstrate the array assignment-routing flow. One is a case of two targets with a ratio of 1:1 and another is a case of multiple targets with continuous ratio of 1:2:16:45. It is shown that both the final results are very close to the desired, where the target and parasitic capacitances are extracted from post-layouts by Calibre and they are fed into SPICE to verify the desired ratios. A switched-capacitor filter with three target capacitors of the values of 3 pF, 4 pF and 5 pF is used to leverage the compensation effect for yield improvement by re-adjusting the fraction of unit-capacitor after routing.
|| X. Jinjun, V. Zolotov, and H. Lei, “Robust Extraction of Spatial Correlation,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 193-202, Apr. 2007.|
 A. Hastings and R. A. Hastings, The Art of Analog Layout, Prentice Hall, 2000.
 M. J. McNutt, S. LeMarquis, and J. L. Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE Journal Solid-State Circuits, pp. 611-616, May 1994.
 P. W. Luo, J. E Chen, C. L. Wey, L. C. Cheng, J. J. Chen and W. C. Wu, “Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 2097-2101, Nov. 2008.
 J. E Chen, P. W. Luo and C. L. Wey, “Yield evaluation of analog placement with arbitrary capacitor ratio,” IEEE International Symposium on Quality of Electronic Design, pp. 179-184, Mar. 2009.
 D. Khalil, M. Dessouky, V. Bourguet, M. M. Louerat, A. Catheline and H. Ragai, “Evaluation of Capacitance Ratios in Automated Accurate Cmmon-Centroid Capacitance Arrays,” IEEE International Symposium on Quality of Electronic Design, pp. 143-147, Mar. 2005.
 D. Khalil and M. Dessouky. “Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio,” Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 576-580, Mar. 2002.
 M. F. Lan, A. Tammineedi and R. Geiger. “Current Mirror Layout Strategies for Enhancing Matching Performance,” Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, pp. 9-26, Jul. 2001.
 C. S. G. Conroy, W. A. Lane, and M. A. Moran, “Statistical Design Techniques for D/A Converters,” IEEE Journal of Solid-State Circuits, pp. 1118-1128, Aug 1989.
 M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, pp. 1433-1439, Oct 1989
 Laker User Guide and Tutorial, Nov. 2003.
 Laker TCL Reference, Nov. 2003.
 B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill, 2001.
 Clif Flynt, Tcl/Tk: A Developer's Guide, Morgan Kaufmann, 2003.
 D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley and Sons, Inc. , 1997
 L. Zhang, R. Raut, Y. Jiang, and U. Kleine. “Placement algorithm in analog-layout designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.1889–1903, Oct. 2006.