博碩士論文 975201030 詳細資訊

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姓名 曾煥程(Huan-cheng Tseng)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於電容陣列區塊之維持比值良率的通道繞線法
(A Yield-aware Ratio-keeping Channel Router for Capacitor Array Block Creation)
★ E2T-iSEE:應用於事件與情感狀態轉移排程器之編輯★ “偶”:具情感之球型機器人
★ 陣列區塊電容產生器於製程設計套件之評量★ 應用於數位家庭整合計畫影像傳輸子系統之設計考量與實現
★ LED 背光模組靜電放電路徑★ 電阻串連式連續參考值產生器於製程設計套件之評量
★ 短篇故事分類與敘述★ 用於類比/混和訊號積體電路可靠度增強的加壓測試
★ 延伸考慮製程參數相關性之類比電路階層式變異數分析器★ 以電子電路觀點對田口式惠斯登電橋模擬實例的再分析
★ 應用於交換電容ΔΣ調變電路之電容排列良率自動化擺置平台★ 陣列MiM電容的自動化佈局
★ 陣列MiM電容的平衡接點之通道繞線法★ 氣象資訊達人
★ 嵌入式WHDVI多核心Forth微控制器之設計★ 使用於矽穿孔耦合分析之垂直十字鏈基板結構
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摘要(中) 隨著半導體製程技術的演進,製程變動(process variation)所造成元件之間的不匹配(mismatch)與導線寄生效應(parasitic effect)的相對應變異也越來越嚴重。然而在類比電路上為了降低設計時的高錯誤率、高複雜度及容易出錯的佈局操作所花費的時間與繁瑣的任務和昂貴的設計成本,所以佈局的自動化設計將成為類比設計過程中一個關鍵的角色。且由於敏感的寄生電容效應、元件的不匹配、製程變動與梯度效應都將導致佈局結果可能是一個不好的佈局,也造成了產品的不準確性與良率的降低。多數類比電路像是類比數位/數位類比轉換器或濾波器等等,其性能都依賴於準確的電容比值。對於要求準確的電容比值大都會使用多顆單位電容並聯取代單一顆大電容並考慮繞線引起的寄生效應,以減少一些不匹配的影響。
摘要(英) As the evolution of semiconductor process technology, the process variation will be more and more serious in device mismatch and wire parasitic. Layout automation is likely to play a key role in analog circuit design to prevent design errors, high complex, error-prone layout tasks, time-consuming, tedious and expensive design iterations. Poor layout due to its sensitivity to parasitic capacitance, device mismatching, process variations and gradient errors will result in both the product inaccuracy and yield loss. The performance of many types of analog circuits, like ADC, DAC, filters, etc., relies on the implementation of accurate capacitor array ratios, which are determined by properly arranging the identical unit-size capacitors and considering the effect of routing induced capacitances.
In this thesis, a yield-aware ratio-keeping channel router is proposed for capacitor array block creation. The 4-step channel router including channel allocation, wire establishment, wire link, and plate outstretching, is performed ordinarily to balance the routing wire length and the number of wire contact via’s of the corresponding array capacitors and to reduce the parasitic capacitances due to extra insertions and overlapping. The router can be not only applied to the case of a pair of two target capacitors but also to the one of multiple target capacitors. By the conjunction of an array assignment using of spatial correlation feature, two cases are used as examples to demonstrate the array assignment-routing flow. One is a case of two targets with a ratio of 1:1 and another is a case of multiple targets with continuous ratio of 1:2:16:45. It is shown that both the final results are very close to the desired, where the target and parasitic capacitances are extracted from post-layouts by Calibre and they are fed into SPICE to verify the desired ratios. A switched-capacitor filter with three target capacitors of the values of 3 pF, 4 pF and 5 pF is used to leverage the compensation effect for yield improvement by re-adjusting the fraction of unit-capacitor after routing.
關鍵字(中) ★ 良率
★ 比值
★ 佈局自動化
關鍵字(英) ★ layout automation
★ yield-aware
★ ratio-keeping
論文目次 中文摘要i
誌 謝iii
第一章 緒論1
1.1 動機與背景1
1.2 論文組織3
第二章 電容佈局設計的概念4
2.2 電容不匹配的原因7
2.3 電容匹配的規則9
第三章 電容陣列的擺放12
3.1 共質心 (Common-Centroid)12
3.2 空間相關性 (Spatial Correlation)14
3.2.1 相關性(correlation)與元件不匹配(mismatch)18
3.2.2 電容比值的變異數(variance)與相關性(correlation)20
第四章 電容陣列的繞線24
4.1 繞線 (Routing)24
4.1.1 設計規範 (Design Rule)26
4.1.2 Ratio-keeping Channel Routing27
4.2 繞線產生的影響31
4.2.1 寄生電容31
4.2.2 繞線的寄生電容33 耦合寄生電容值的影響34 導線寄生電容值的評估36
第五章 實驗及分析39
5.1 自動化實體佈局的實現39
5.2 電容比值的測量43
5.2.1 電容的擺放與繞線範例分析43
5.2.2 交換式電容電路49 模擬結果50
第六章 結論59
參考文獻 [1] X. Jinjun, V. Zolotov, and H. Lei, “Robust Extraction of Spatial Correlation,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 193-202, Apr. 2007.
[2] A. Hastings and R. A. Hastings, The Art of Analog Layout, Prentice Hall, 2000.
[3] M. J. McNutt, S. LeMarquis, and J. L. Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE Journal Solid-State Circuits, pp. 611-616, May 1994.
[4] P. W. Luo, J. E Chen, C. L. Wey, L. C. Cheng, J. J. Chen and W. C. Wu, “Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 2097-2101, Nov. 2008.
[5] J. E Chen, P. W. Luo and C. L. Wey, “Yield evaluation of analog placement with arbitrary capacitor ratio,” IEEE International Symposium on Quality of Electronic Design, pp. 179-184, Mar. 2009.
[6] D. Khalil, M. Dessouky, V. Bourguet, M. M. Louerat, A. Catheline and H. Ragai, “Evaluation of Capacitance Ratios in Automated Accurate Cmmon-Centroid Capacitance Arrays,” IEEE International Symposium on Quality of Electronic Design, pp. 143-147, Mar. 2005.
[7] D. Khalil and M. Dessouky. “Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio,” Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 576-580, Mar. 2002.
[8] M. F. Lan, A. Tammineedi and R. Geiger. “Current Mirror Layout Strategies for Enhancing Matching Performance,” Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, pp. 9-26, Jul. 2001.
[9] C. S. G. Conroy, W. A. Lane, and M. A. Moran, “Statistical Design Techniques for D/A Converters,” IEEE Journal of Solid-State Circuits, pp. 1118-1128, Aug 1989.
[10] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, pp. 1433-1439, Oct 1989
[11] Laker User Guide and Tutorial, Nov. 2003.
[12] Laker TCL Reference, Nov. 2003.
[13] B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill, 2001.
[14] Clif Flynt, Tcl/Tk: A Developer's Guide, Morgan Kaufmann, 2003.
[15] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley and Sons, Inc. , 1997
[16] L. Zhang, R. Raut, Y. Jiang, and U. Kleine. “Placement algorithm in analog-layout designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.1889–1903, Oct. 2006.
指導教授 魏慶隆、梁新聰、陳竹一
(Chin-Long Wey、Hsing-Chung Liang、Jwu-E Chen)
審核日期 2010-11-3
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